IEICE TRANSACTIONS on Electronics
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness
Summary :
This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.3 pp.344-347
- Publication Date
- 2017/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.344
- Type of Manuscript
- BRIEF PAPER
- Category
- Semiconductor Materials and Devices
Authors
Yuan WANG
Peking University
Guangyi LU
Peking University
Yize WANG
Peking University
Xing ZHANG
Peking University
Keyword
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Yuan WANG, Guangyi LU, Yize WANG, Xing ZHANG, "Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 3, pp. 344-347, March 2017, doi: 10.1587/transele.E100.C.344.
Abstract: This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.344/_p
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@ARTICLE{e100-c_3_344,
author={Yuan WANG, Guangyi LU, Yize WANG, Xing ZHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness},
year={2017},
volume={E100-C},
number={3},
pages={344-347},
abstract={This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.},
keywords={},
doi={10.1587/transele.E100.C.344},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness
T2 - IEICE TRANSACTIONS on Electronics
SP - 344
EP - 347
AU - Yuan WANG
AU - Guangyi LU
AU - Yize WANG
AU - Xing ZHANG
PY - 2017
DO - 10.1587/transele.E100.C.344
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2017
AB - This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.
ER -
English
