A frequency-reconfigurable dipole antenna, whose dual resonant frequencies are independently controlled, is introduced. The antenna's conductor consists of radiating conductors, lumped and distributed elements, and varactors. To design the antenna, current distribution, input impedance, and radiation power including higher-order modes, are analyzed for a narrow-angle sectorial antenna embedded with passive elements. To derive the formulae used, radiation power is analyzed in two ways: using Chu's equivalent circuit and the multipole expansion method. Numerical estimations of electrically small antennas show that dual-band antennas are feasible. The dual resonant frequencies are controlled with the embedded series and shunt inductors. A dual-band antenna is fabricated, and measured input impedances agree well with the calculated data. With the configuration, an electrically small 2.5-/5-GHz dual-band reconfig-urable antenna is designed and fabricated, where the reactance values for the series and shunt inductors are controlled with varactors, each connected in series to the inductors. Varying the voltages applied to the varactors varies the measured upper and lower resonant frequencies between 2.6 and 2.9GHz and between 5.1 and 5.3GHz, where the other resonant frequency is kept almost identical. Measured radiation patterns on the H-plane are almost omni-directional for both bands.

This paper overviews the history of a class of varactor tuned bandpass filters. Since the miniaturization as well as the high performance of the tunable bandpass filters is required for the next generation mobile communication systems, the discussion is focused on the various planar type tunable filters including active configurations. Brief design concepts of various tunable filter configurations as well as their characteristics are discussed.

This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-µm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18-214) MHz at 3.3 V with peak-to-peak (Pk-Pk) jitter of less than 70 ps at 192 MHz/3.3 V.