This paper presents an automatic gain control (AGC) system suitable for 60GHz direct conversion receivers. By using a two step gain control algorithm with high-pass filter cutoff frequency switching, the proposed AGC system realizes fast settling time and wide dynamic range simultaneously. The paper also discusses wide-bandwidth variable gain amplifier (VGA) design. By introducing digitally-controlled resistors and gain flattening capacitors, the proposed VGA realizes wide gain range while compensating gain variations due to parasitic capacitance of MOS switches. The AGC system is implemented in a transceiver chipset where RFIC and BBIC are fabricated in 90nm CMOS and 40nm CMOS respectively. The measurement shows excellent dynamic range of 47dB with +/-1dB gain accuracy within 1µs settling time, which satisfies the stringent requirements of the IEEE802.11ad standard.

This paper reports a current-reused pseudo-differential (CRPD) programmable gain amplifier (PGA) that demonstrates small size, low power, wide band, low noise, and high linearity operation with 4 control bits. Implemented in 0.18um CMOS technology, the PGA shows the gain range from -9.9 to 8.3 dB with gain error of less than 0.38 dB. The IIP3, P1 dB, and smallest 3-dB bandwidth are 10.5 to 27 dBm, -9 to 9.5 dBm, and 250 MHz, respectively. The PGA occupies the chip area of 0.04 mm2 and consumes only 460 µA from a 1.2 V supply.

Two variable gain amplifiers (VGAs) that adopt new approximated exponential equations are proposed in this paper. The dB-linear range of the proposed VGAs is extended more than what the approximated exponential equations predict by a bias circuit technique that adopts negative feedback. The proposed VGAs feature wide gain variation, low-power, high linearity, wide control signal range, and small chip size. One of the proposed VGAs is fabricated in 0.18 µm CMOS technology and measurements show a gain variation of 83 dB (-3647 dB) with a gain error of less than 2 dB, and P1 dB/IIP3 from -55/8 to -20/20.5 dBm, while consuming an average current of 3.4 mA from a 1.8 V supply; the chip occupies 0.4 mm2. The other VGA is simulated in 0.18 µm CMOS technology and simulations show a gain variation of 91 dB (-4150 dB), and P1 dB/IIP3 from -50/-25 to -33/0 dBm, while consuming an average current of 1.5 mA from a 1.8 V supply.

An all CMOS variable gain amplifier (VGA) which features wide dB-linear gain range per stage (45 dB), low power consumption (1.32 mW), small chip size (0.13 mm2), and low supply voltage (1.2 V) is described. The dB-linear range is extended by reducing the supply voltage of the conventional V-to-I converter. The two-stage VGA implemented in 0.18 µm CMOS offers 90 dB of gain variation, 3 dB bandwidth of greater than 21 MHz, and max/min input IP3 and P1 dB, respectively, of -5/-42 and -12/-50 dBm.