Due to large capacitance, high access ratio and wide access bitwidth, frame memory is one of the most energy consuming devices in modern video encoders. This paper proposes a new architectural technique to reduce energy dissipation of frame memory through adaptive bitwith compression. Unlike related approaches, the technique utilizes the fixed order of memory accesses and data correlation of video sequences, by dynamically adjusting the memory bitwidth to the number of bits changed per pixel. Instead of treating the data bits independently, we group the most significant bits together, activating the corresponding group of bit-lines adaptively to data variation. The approach is not restricted to the specific bit-patterns nor depends on the storage phase. It works equally well on read and write accesses, as well as during precharging. Simulations show that using this method we can reduce the total energy consumption of the frame memory cell array by 20% without affecting the picture quality. The implementation scheme is simple yet compact.

This paper describes the architecture and new circuit technologies of a proposed Pixel (bit) -Aligned Triple-port DRAM (PATDRAM). The PATDRAM has a 270 K word 16 b Random Access Memory (RAM), a 512 word 8 b Serial Access Memory-(a) (SAMa) and a 1024 word 4 b Serial Access Memory-(b) (SAMb). The random port, serial-a and serial-b port can be operated by three independent synchronous clocks. In these three ports, word data can be aligned to the location of an arbitrary bit position. Data transfer from SAMb to RAM can be individually masked by transfer mask data. The RAM operates by 33 MHz synchronous clock and two SAMs operate by 40 MHz clocks. Novel architecture of the PATDRAM accelerates graphics performance and simplifies in multimedia systems which manage both realtime video and computer graphics data, and also accelerates graphics performance in both two-dimensional (2D) and three-dimensional (3D) graphics systems. PATDRAM was designed using a 0.6 µ double metal, triple poly, stacked capacitor, CMOS process technology in a 10.98 mm9.88 mm die area integrated 4.4 Mb RAM, 8 Kb SAM, 4 Kb transfer mask register and 5 Kgate logic.