IEICE TRANSACTIONS on Communications
An Adaptive Reed-Solomon Decoder Using Separate Clocks in the Pipelined Steps
Summary :
In this paper, an efficient architecture for an adaptive Reed-Solomon decoder is presented, where the block length n and the message length k can be varied from their minimum allowable values up to their selected values. This eliminates the need of inserting zeros before decoding shortened RS codes. And the error-correcting capability t can be changed adaptively to channel state at every codeword block. The decoder allows efficient decoding in both burst mode and continuous mode, and it permits 3-step pipelined processing based on the modified Euclid's algorithm. Each step in decoding is designed to be clocked by a separate clock. Thus, each step can be efficiently pipelined with no help of multiplexing. Also, it makes it possible to employ no additional buffer even when the decoder input and output clocks are different. The adaptive RS decoder over GF(28) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip. It can be used in a wide range of applications because of its versatility.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E88-B No.2 pp.615-622
- Publication Date
- 2005/02/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietcom/e88-b.2.615
- Type of Manuscript
- PAPER
- Category
- Devices/Circuits for Communications
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Keyword
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Moon-Kyou SONG, Min-Han KONG, "An Adaptive Reed-Solomon Decoder Using Separate Clocks in the Pipelined Steps" in IEICE TRANSACTIONS on Communications,
vol. E88-B, no. 2, pp. 615-622, February 2005, doi: 10.1093/ietcom/e88-b.2.615.
Abstract: In this paper, an efficient architecture for an adaptive Reed-Solomon decoder is presented, where the block length n and the message length k can be varied from their minimum allowable values up to their selected values. This eliminates the need of inserting zeros before decoding shortened RS codes. And the error-correcting capability t can be changed adaptively to channel state at every codeword block. The decoder allows efficient decoding in both burst mode and continuous mode, and it permits 3-step pipelined processing based on the modified Euclid's algorithm. Each step in decoding is designed to be clocked by a separate clock. Thus, each step can be efficiently pipelined with no help of multiplexing. Also, it makes it possible to employ no additional buffer even when the decoder input and output clocks are different. The adaptive RS decoder over GF(28) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip. It can be used in a wide range of applications because of its versatility.
URL: https://global.ieice.org/en_transactions/communications/10.1093/ietcom/e88-b.2.615/_p
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@ARTICLE{e88-b_2_615,
author={Moon-Kyou SONG, Min-Han KONG, },
journal={IEICE TRANSACTIONS on Communications},
title={An Adaptive Reed-Solomon Decoder Using Separate Clocks in the Pipelined Steps},
year={2005},
volume={E88-B},
number={2},
pages={615-622},
abstract={In this paper, an efficient architecture for an adaptive Reed-Solomon decoder is presented, where the block length n and the message length k can be varied from their minimum allowable values up to their selected values. This eliminates the need of inserting zeros before decoding shortened RS codes. And the error-correcting capability t can be changed adaptively to channel state at every codeword block. The decoder allows efficient decoding in both burst mode and continuous mode, and it permits 3-step pipelined processing based on the modified Euclid's algorithm. Each step in decoding is designed to be clocked by a separate clock. Thus, each step can be efficiently pipelined with no help of multiplexing. Also, it makes it possible to employ no additional buffer even when the decoder input and output clocks are different. The adaptive RS decoder over GF(28) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip. It can be used in a wide range of applications because of its versatility.},
keywords={},
doi={10.1093/ietcom/e88-b.2.615},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - An Adaptive Reed-Solomon Decoder Using Separate Clocks in the Pipelined Steps
T2 - IEICE TRANSACTIONS on Communications
SP - 615
EP - 622
AU - Moon-Kyou SONG
AU - Min-Han KONG
PY - 2005
DO - 10.1093/ietcom/e88-b.2.615
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E88-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2005
AB - In this paper, an efficient architecture for an adaptive Reed-Solomon decoder is presented, where the block length n and the message length k can be varied from their minimum allowable values up to their selected values. This eliminates the need of inserting zeros before decoding shortened RS codes. And the error-correcting capability t can be changed adaptively to channel state at every codeword block. The decoder allows efficient decoding in both burst mode and continuous mode, and it permits 3-step pipelined processing based on the modified Euclid's algorithm. Each step in decoding is designed to be clocked by a separate clock. Thus, each step can be efficiently pipelined with no help of multiplexing. Also, it makes it possible to employ no additional buffer even when the decoder input and output clocks are different. The adaptive RS decoder over GF(28) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip. It can be used in a wide range of applications because of its versatility.
ER -
English
