IEICE TRANSACTIONS on Communications
Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits
Summary :
As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E90-B No.7 pp.1826-1834
- Publication Date
- 2007/07/01
- Publicized
- Online ISSN
- 1745-1345
- DOI
- 10.1093/ietcom/e90-b.7.1826
- Type of Manuscript
- PAPER
- Category
- Energy in Electronics Communications
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Keyword
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Hyunchul SHIN, Changhee LEE, "Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits" in IEICE TRANSACTIONS on Communications,
vol. E90-B, no. 7, pp. 1826-1834, July 2007, doi: 10.1093/ietcom/e90-b.7.1826.
Abstract: As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.
URL: https://global.ieice.org/en_transactions/communications/10.1093/ietcom/e90-b.7.1826/_p
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@ARTICLE{e90-b_7_1826,
author={Hyunchul SHIN, Changhee LEE, },
journal={IEICE TRANSACTIONS on Communications},
title={Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits},
year={2007},
volume={E90-B},
number={7},
pages={1826-1834},
abstract={As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.},
keywords={},
doi={10.1093/ietcom/e90-b.7.1826},
ISSN={1745-1345},
month={July},}
Copy
TY - JOUR
TI - Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits
T2 - IEICE TRANSACTIONS on Communications
SP - 1826
EP - 1834
AU - Hyunchul SHIN
AU - Changhee LEE
PY - 2007
DO - 10.1093/ietcom/e90-b.7.1826
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E90-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 2007
AB - As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.
ER -
English
