In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900 K gates, two DSPs with maximum 8,000 MIPS at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.
OFDM, IEEE 802.16, FPGA, DSP, platform
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Byung Wook LEE, Sung Ho CHO, "A Design of the Signal Processing Hardware Platform for Communication Systems" in IEICE TRANSACTIONS on Communications,
vol. E91-B, no. 3, pp. 939-942, March 2008, doi: 10.1093/ietcom/e91-b.3.939.
Abstract: In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900 K gates, two DSPs with maximum 8,000 MIPS at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.
URL: https://global.ieice.org/en_transactions/communications/10.1093/ietcom/e91-b.3.939/_p
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@ARTICLE{e91-b_3_939,
author={Byung Wook LEE, Sung Ho CHO, },
journal={IEICE TRANSACTIONS on Communications},
title={A Design of the Signal Processing Hardware Platform for Communication Systems},
year={2008},
volume={E91-B},
number={3},
pages={939-942},
abstract={In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900 K gates, two DSPs with maximum 8,000 MIPS at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.},
keywords={},
doi={10.1093/ietcom/e91-b.3.939},
ISSN={1745-1345},
month={March},}
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TY - JOUR
TI - A Design of the Signal Processing Hardware Platform for Communication Systems
T2 - IEICE TRANSACTIONS on Communications
SP - 939
EP - 942
AU - Byung Wook LEE
AU - Sung Ho CHO
PY - 2008
DO - 10.1093/ietcom/e91-b.3.939
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E91-B
IS - 3
JA - IEICE TRANSACTIONS on Communications
Y1 - March 2008
AB - In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900 K gates, two DSPs with maximum 8,000 MIPS at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.
ER -