Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna
Summary :
We have proposed a digital beamforming (DBF) self-beam-steering array antenna which features maximal ratio combining enabling it to efficiently use the received power or to rapidly track the desired signal. The DBF self-beam-steering array antenna utilizes digital signal processing with an active array antenna configuration. ASIC implementation of the digital signal processor is inevitable for DBF antenna application in practical mobile communications environments. In this paper, we present a scheme for implementing a digital signal processor in ASICs using ten FPGAs (Field Programmable Gate Arrays) for the DBF self-beam-steering array antenna. Results of some experiments obtained in a large radio anechoic chamber are shown to confirm a basic function of the system.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E80-B No.1 pp.166-175
- Publication Date
- 1997/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Antennas and Propagation
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Toyohisa TANAKA, Ryu MIURA, Yoshio KARASAWA, "Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna" in IEICE TRANSACTIONS on Communications,
vol. E80-B, no. 1, pp. 166-175, January 1997, doi: .
Abstract: We have proposed a digital beamforming (DBF) self-beam-steering array antenna which features maximal ratio combining enabling it to efficiently use the received power or to rapidly track the desired signal. The DBF self-beam-steering array antenna utilizes digital signal processing with an active array antenna configuration. ASIC implementation of the digital signal processor is inevitable for DBF antenna application in practical mobile communications environments. In this paper, we present a scheme for implementing a digital signal processor in ASICs using ten FPGAs (Field Programmable Gate Arrays) for the DBF self-beam-steering array antenna. Results of some experiments obtained in a large radio anechoic chamber are shown to confirm a basic function of the system.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e80-b_1_166/_p
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@ARTICLE{e80-b_1_166,
author={Toyohisa TANAKA, Ryu MIURA, Yoshio KARASAWA, },
journal={IEICE TRANSACTIONS on Communications},
title={Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna},
year={1997},
volume={E80-B},
number={1},
pages={166-175},
abstract={We have proposed a digital beamforming (DBF) self-beam-steering array antenna which features maximal ratio combining enabling it to efficiently use the received power or to rapidly track the desired signal. The DBF self-beam-steering array antenna utilizes digital signal processing with an active array antenna configuration. ASIC implementation of the digital signal processor is inevitable for DBF antenna application in practical mobile communications environments. In this paper, we present a scheme for implementing a digital signal processor in ASICs using ten FPGAs (Field Programmable Gate Arrays) for the DBF self-beam-steering array antenna. Results of some experiments obtained in a large radio anechoic chamber are shown to confirm a basic function of the system.},
keywords={},
doi={},
ISSN={},
month={January},}
Copy
TY - JOUR
TI - Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna
T2 - IEICE TRANSACTIONS on Communications
SP - 166
EP - 175
AU - Toyohisa TANAKA
AU - Ryu MIURA
AU - Yoshio KARASAWA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E80-B
IS - 1
JA - IEICE TRANSACTIONS on Communications
Y1 - January 1997
AB - We have proposed a digital beamforming (DBF) self-beam-steering array antenna which features maximal ratio combining enabling it to efficiently use the received power or to rapidly track the desired signal. The DBF self-beam-steering array antenna utilizes digital signal processing with an active array antenna configuration. ASIC implementation of the digital signal processor is inevitable for DBF antenna application in practical mobile communications environments. In this paper, we present a scheme for implementing a digital signal processor in ASICs using ten FPGAs (Field Programmable Gate Arrays) for the DBF self-beam-steering array antenna. Results of some experiments obtained in a large radio anechoic chamber are shown to confirm a basic function of the system.
ER -
English
