A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems

Toshiaki TAKAO; Yoshifumi SUZUKI; Tadashi SHIRATO

A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems

Toshiaki TAKAO, Yoshifumi SUZUKI, Tadashi SHIRATO

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We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.

Publication: IEICE TRANSACTIONS on Communications Vol.E82-B No.8 pp.1326-1333

Publication Date: 1999/08/25

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Type of Manuscript: PAPER

Category: Communication Device and Circuit

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Toshiaki TAKAO, Yoshifumi SUZUKI, Tadashi SHIRATO, "A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems" in IEICE TRANSACTIONS on Communications, vol. E82-B, no. 8, pp. 1326-1333, August 1999, doi: .
Abstract: We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e82-b_8_1326/_p

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@ARTICLE{e82-b_8_1326,
author={Toshiaki TAKAO, Yoshifumi SUZUKI, Tadashi SHIRATO, },
journal={IEICE TRANSACTIONS on Communications},
title={A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems},
year={1999},
volume={E82-B},
number={8},
pages={1326-1333},
abstract={We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems
T2 - IEICE TRANSACTIONS on Communications
SP - 1326
EP - 1333
AU - Toshiaki TAKAO
AU - Yoshifumi SUZUKI
AU - Tadashi SHIRATO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E82-B
IS - 8
JA - IEICE TRANSACTIONS on Communications
Y1 - August 1999
AB - We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.
ER -