Design of DS1 Transport Device in SDH Network

Yeong-Gang SHOW; Kuo-Bing CHOU; Jim WANG; Kou-Tan WU

Design of DS1 Transport Device in SDH Network

Yeong-Gang SHOW, Kuo-Bing CHOU, Jim WANG, Kou-Tan WU

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Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) are the standards for lightwave transmission systems, which can accommodate various existing signal types via Tributary Units (TUs) or Virtual Tributaries (VTs). In the SDH standards, Tributary Unit-11 (TU-11) is used to transport the DS1 signal with payload pointer and path overheads. In this paper, asynchronous floating mode TU-11 Mapper is designed by FPGAs for transmit and receive devices. The DS1 signal is mapped into TU-11 frame, and through Combus interface, then directly added/dropped into/from the VC-4 payload by taking advantage of the byte order frame format of SDH. In the add direction, a synchronizer with efficient stuffing algorithm is designed to minimize the waiting time jitter and absorb the frequency offset, the instantaneous jitter, the wander, and the gap of TU-11 data payload. In the drop direction, a desynchronizer implemented by a novel all digital phase locked loop and FIFO is used to accommodate the effect of irregular spacing of frame format and jitters generated by the pointer movement and bit justification. A prototype circuit board is built with the designed TU-11 Mapper and embedded in an STM-1 ADM system for long term testing.

Publication: IEICE TRANSACTIONS on Communications Vol.E83-B No.7 pp.1389-1399

Publication Date: 2000/07/25

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Type of Manuscript: PAPER

Category: Fiber-Optic Transmission

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Yeong-Gang SHOW, Kuo-Bing CHOU, Jim WANG, Kou-Tan WU, "Design of DS1 Transport Device in SDH Network" in IEICE TRANSACTIONS on Communications, vol. E83-B, no. 7, pp. 1389-1399, July 2000, doi: .
Abstract: Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) are the standards for lightwave transmission systems, which can accommodate various existing signal types via Tributary Units (TUs) or Virtual Tributaries (VTs). In the SDH standards, Tributary Unit-11 (TU-11) is used to transport the DS1 signal with payload pointer and path overheads. In this paper, asynchronous floating mode TU-11 Mapper is designed by FPGAs for transmit and receive devices. The DS1 signal is mapped into TU-11 frame, and through Combus interface, then directly added/dropped into/from the VC-4 payload by taking advantage of the byte order frame format of SDH. In the add direction, a synchronizer with efficient stuffing algorithm is designed to minimize the waiting time jitter and absorb the frequency offset, the instantaneous jitter, the wander, and the gap of TU-11 data payload. In the drop direction, a desynchronizer implemented by a novel all digital phase locked loop and FIFO is used to accommodate the effect of irregular spacing of frame format and jitters generated by the pointer movement and bit justification. A prototype circuit board is built with the designed TU-11 Mapper and embedded in an STM-1 ADM system for long term testing.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e83-b_7_1389/_p

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@ARTICLE{e83-b_7_1389,
author={Yeong-Gang SHOW, Kuo-Bing CHOU, Jim WANG, Kou-Tan WU, },
journal={IEICE TRANSACTIONS on Communications},
title={Design of DS1 Transport Device in SDH Network},
year={2000},
volume={E83-B},
number={7},
pages={1389-1399},
abstract={Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) are the standards for lightwave transmission systems, which can accommodate various existing signal types via Tributary Units (TUs) or Virtual Tributaries (VTs). In the SDH standards, Tributary Unit-11 (TU-11) is used to transport the DS1 signal with payload pointer and path overheads. In this paper, asynchronous floating mode TU-11 Mapper is designed by FPGAs for transmit and receive devices. The DS1 signal is mapped into TU-11 frame, and through Combus interface, then directly added/dropped into/from the VC-4 payload by taking advantage of the byte order frame format of SDH. In the add direction, a synchronizer with efficient stuffing algorithm is designed to minimize the waiting time jitter and absorb the frequency offset, the instantaneous jitter, the wander, and the gap of TU-11 data payload. In the drop direction, a desynchronizer implemented by a novel all digital phase locked loop and FIFO is used to accommodate the effect of irregular spacing of frame format and jitters generated by the pointer movement and bit justification. A prototype circuit board is built with the designed TU-11 Mapper and embedded in an STM-1 ADM system for long term testing.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Design of DS1 Transport Device in SDH Network
T2 - IEICE TRANSACTIONS on Communications
SP - 1389
EP - 1399
AU - Yeong-Gang SHOW
AU - Kuo-Bing CHOU
AU - Jim WANG
AU - Kou-Tan WU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E83-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 2000
AB - Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) are the standards for lightwave transmission systems, which can accommodate various existing signal types via Tributary Units (TUs) or Virtual Tributaries (VTs). In the SDH standards, Tributary Unit-11 (TU-11) is used to transport the DS1 signal with payload pointer and path overheads. In this paper, asynchronous floating mode TU-11 Mapper is designed by FPGAs for transmit and receive devices. The DS1 signal is mapped into TU-11 frame, and through Combus interface, then directly added/dropped into/from the VC-4 payload by taking advantage of the byte order frame format of SDH. In the add direction, a synchronizer with efficient stuffing algorithm is designed to minimize the waiting time jitter and absorb the frequency offset, the instantaneous jitter, the wander, and the gap of TU-11 data payload. In the drop direction, a desynchronizer implemented by a novel all digital phase locked loop and FIFO is used to accommodate the effect of irregular spacing of frame format and jitters generated by the pointer movement and bit justification. A prototype circuit board is built with the designed TU-11 Mapper and embedded in an STM-1 ADM system for long term testing.
ER -