155-Mb/s Burst-Mode Clock Recovery Circuit Using the Jitter Reduction Technique
Summary :
We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E86-B No.4 pp.1423-1426
- Publication Date
- 2003/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Fiber-Optic Transmission
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Jae-Seung HWANG, Chul-Soo PARK, Chang-Soo PARK, "155-Mb/s Burst-Mode Clock Recovery Circuit Using the Jitter Reduction Technique" in IEICE TRANSACTIONS on Communications,
vol. E86-B, no. 4, pp. 1423-1426, April 2003, doi: .
Abstract: We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e86-b_4_1423/_p
Copy
@ARTICLE{e86-b_4_1423,
author={Jae-Seung HWANG, Chul-Soo PARK, Chang-Soo PARK, },
journal={IEICE TRANSACTIONS on Communications},
title={155-Mb/s Burst-Mode Clock Recovery Circuit Using the Jitter Reduction Technique},
year={2003},
volume={E86-B},
number={4},
pages={1423-1426},
abstract={We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - 155-Mb/s Burst-Mode Clock Recovery Circuit Using the Jitter Reduction Technique
T2 - IEICE TRANSACTIONS on Communications
SP - 1423
EP - 1426
AU - Jae-Seung HWANG
AU - Chul-Soo PARK
AU - Chang-Soo PARK
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E86-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2003
AB - We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.
ER -
English
