IEICE TRANSACTIONS on Communications
Implementation of a Two-Step SOVA Decoder with a Fixed Scaling Factor
Summary :
Two implementation schemes for a two-step SOVA (Soft Output Viterbi Algorithm) decoder are proposed and verified in a chip. One uses the combination of trace back (TB) logic to find the survivor state and double trace back logic to find the weighting factor of a two-step SOVA. The other is that the reliability values are divided by a scaling factor in order to compensate for the distortion brought by overestimating those values in SOVA. We introduced a fixed scaling factor of 0.25 or 0.33 for a rate 1/3 and designed an 8-state Turbo decoder with a 256-bit frame size to lower the reliability values. The implemented architecture of the two-step SOVA decoder allows important savings in area and high-speed processing compared with the one-step SOVA decoder using register exchange (RE) or trace-back (TB) method. The chip is fabricated using 0.65 µm gate array at Samsung Electronics and it shows higher SNR performance by 2 dB at the BER 10-4 than that of a two-step SOVA decoder without a scaling factor.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E86-B No.6 pp.1893-1900
- Publication Date
- 2003/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Wireless Communication Technology
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Taek-Won KWON, Jun-Rim CHOI, "Implementation of a Two-Step SOVA Decoder with a Fixed Scaling Factor" in IEICE TRANSACTIONS on Communications,
vol. E86-B, no. 6, pp. 1893-1900, June 2003, doi: .
Abstract: Two implementation schemes for a two-step SOVA (Soft Output Viterbi Algorithm) decoder are proposed and verified in a chip. One uses the combination of trace back (TB) logic to find the survivor state and double trace back logic to find the weighting factor of a two-step SOVA. The other is that the reliability values are divided by a scaling factor in order to compensate for the distortion brought by overestimating those values in SOVA. We introduced a fixed scaling factor of 0.25 or 0.33 for a rate 1/3 and designed an 8-state Turbo decoder with a 256-bit frame size to lower the reliability values. The implemented architecture of the two-step SOVA decoder allows important savings in area and high-speed processing compared with the one-step SOVA decoder using register exchange (RE) or trace-back (TB) method. The chip is fabricated using 0.65 µm gate array at Samsung Electronics and it shows higher SNR performance by 2 dB at the BER 10-4 than that of a two-step SOVA decoder without a scaling factor.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e86-b_6_1893/_p
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@ARTICLE{e86-b_6_1893,
author={Taek-Won KWON, Jun-Rim CHOI, },
journal={IEICE TRANSACTIONS on Communications},
title={Implementation of a Two-Step SOVA Decoder with a Fixed Scaling Factor},
year={2003},
volume={E86-B},
number={6},
pages={1893-1900},
abstract={Two implementation schemes for a two-step SOVA (Soft Output Viterbi Algorithm) decoder are proposed and verified in a chip. One uses the combination of trace back (TB) logic to find the survivor state and double trace back logic to find the weighting factor of a two-step SOVA. The other is that the reliability values are divided by a scaling factor in order to compensate for the distortion brought by overestimating those values in SOVA. We introduced a fixed scaling factor of 0.25 or 0.33 for a rate 1/3 and designed an 8-state Turbo decoder with a 256-bit frame size to lower the reliability values. The implemented architecture of the two-step SOVA decoder allows important savings in area and high-speed processing compared with the one-step SOVA decoder using register exchange (RE) or trace-back (TB) method. The chip is fabricated using 0.65 µm gate array at Samsung Electronics and it shows higher SNR performance by 2 dB at the BER 10-4 than that of a two-step SOVA decoder without a scaling factor.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - Implementation of a Two-Step SOVA Decoder with a Fixed Scaling Factor
T2 - IEICE TRANSACTIONS on Communications
SP - 1893
EP - 1900
AU - Taek-Won KWON
AU - Jun-Rim CHOI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E86-B
IS - 6
JA - IEICE TRANSACTIONS on Communications
Y1 - June 2003
AB - Two implementation schemes for a two-step SOVA (Soft Output Viterbi Algorithm) decoder are proposed and verified in a chip. One uses the combination of trace back (TB) logic to find the survivor state and double trace back logic to find the weighting factor of a two-step SOVA. The other is that the reliability values are divided by a scaling factor in order to compensate for the distortion brought by overestimating those values in SOVA. We introduced a fixed scaling factor of 0.25 or 0.33 for a rate 1/3 and designed an 8-state Turbo decoder with a 256-bit frame size to lower the reliability values. The implemented architecture of the two-step SOVA decoder allows important savings in area and high-speed processing compared with the one-step SOVA decoder using register exchange (RE) or trace-back (TB) method. The chip is fabricated using 0.65 µm gate array at Samsung Electronics and it shows higher SNR performance by 2 dB at the BER 10-4 than that of a two-step SOVA decoder without a scaling factor.
ER -
English
