IEICE TRANSACTIONS on Communications
Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches
Summary :
FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E102-B No.9 pp.1862-1874
- Publication Date
- 2019/09/01
- Publicized
- 2019/03/18
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.2018EBP3333
- Type of Manuscript
- PAPER
- Category
- Transmission Systems and Transmission Equipment for Communications
Authors
Junnan LI
National University of Defense Technology
Biao HAN
National University of Defense Technology
Zhigang SUN
National University of Defense Technology
Tao LI
National University of Defense Technology
Xiaoyan WANG
Ibaraki University
Keyword
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Junnan LI, Biao HAN, Zhigang SUN, Tao LI, Xiaoyan WANG, "Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches" in IEICE TRANSACTIONS on Communications,
vol. E102-B, no. 9, pp. 1862-1874, September 2019, doi: 10.1587/transcom.2018EBP3333.
Abstract: FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2018EBP3333/_p
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@ARTICLE{e102-b_9_1862,
author={Junnan LI, Biao HAN, Zhigang SUN, Tao LI, Xiaoyan WANG, },
journal={IEICE TRANSACTIONS on Communications},
title={Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches},
year={2019},
volume={E102-B},
number={9},
pages={1862-1874},
abstract={FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.},
keywords={},
doi={10.1587/transcom.2018EBP3333},
ISSN={1745-1345},
month={September},}
Copy
TY - JOUR
TI - Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches
T2 - IEICE TRANSACTIONS on Communications
SP - 1862
EP - 1874
AU - Junnan LI
AU - Biao HAN
AU - Zhigang SUN
AU - Tao LI
AU - Xiaoyan WANG
PY - 2019
DO - 10.1587/transcom.2018EBP3333
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E102-B
IS - 9
JA - IEICE TRANSACTIONS on Communications
Y1 - September 2019
AB - FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.
ER -
English
