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Since ISAR is widely applied in many occasions and provides high resolution images of the target, ISAR countermeasures are attracting more and more attention. Most of the present methods of deception jamming are not suitable for engineering realization due to the heavy computation load or the large calculation delay. Deception jamming against ISAR requires large computation resource and real-time performance algorithms. Many studies on false target jamming assume that the jammer is able to receive the target echo or transmit the jamming signal to the real target, which is sometimes not possible. How to impose the target property onto the intercepted radar signal is critical to a deception jammer. This paper proposes a jamming algorithm based on parallel convolution and one-bit quantization. The algorithm is able to produce a single false target on ISAR image by the jammer itself. The requirement for computation resource is within the capabilities of current digital signal processors such as FPGA or DSP. The method processes the samples of radar signal in parallel and generates the jamming signal at the rate of ADC data, solving the problem that the real-time performance is not satisfied when the input data rate for convolution is far higher than the clock frequency of FPGA. In order to reduce the computation load of convolution, one-bit quantization is utilized. The complex multiplication is implemented by logical resources, which significantly reduces the consumption of FPGA multipliers. The parallel convolution jamming signal, whose date rate exceeds the FPGA clock rate, is introduced and analyzed in detail. In theory, the bandwidth of jamming signal can be half of the sampling frequency of high speed ADC, making the proposed jamming algorithm able to counter ultra-wideband ISAR signals. The performance and validity of the proposed method are verified by simulations. This jamming method is real-time and capable of producing a false target of large size at the low cost of FPGA device.

- Publication
- IEICE TRANSACTIONS on Communications Vol.E103-B No.5 pp.609-617

- Publication Date
- 2020/05/01

- Publicized
- 2019/11/06

- Online ISSN
- 1745-1345

- DOI
- 10.1587/transcom.2019EBP3109

- Type of Manuscript
- PAPER

- Category
- Sensing

Ning TAI

State Key Laboratory of Complex Electromagnetic Environment Effects on Electronics and Information System (CEMEE)

Huan LIN

Luoyang Electronic Equipment Test Center (LEETC)

Chao WEI

Luoyang Electronic Equipment Test Center (LEETC)

Yongwei LU

Luoyang Electronic Equipment Test Center (LEETC)

Chao WANG

National University of Defense Technology (NUDT)

Kaibo CUI

National University of Defense Technology (NUDT)

ISAR, jamming, convolution, FPGA, LFM

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

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Ning TAI, Huan LIN, Chao WEI, Yongwei LU, Chao WANG, Kaibo CUI, "A Wideband Real-Time Deception Jamming Method for Countering ISAR Based on Parallel Convolution" in IEICE TRANSACTIONS on Communications,
vol. E103-B, no. 5, pp. 609-617, May 2020, doi: 10.1587/transcom.2019EBP3109.

Abstract: Since ISAR is widely applied in many occasions and provides high resolution images of the target, ISAR countermeasures are attracting more and more attention. Most of the present methods of deception jamming are not suitable for engineering realization due to the heavy computation load or the large calculation delay. Deception jamming against ISAR requires large computation resource and real-time performance algorithms. Many studies on false target jamming assume that the jammer is able to receive the target echo or transmit the jamming signal to the real target, which is sometimes not possible. How to impose the target property onto the intercepted radar signal is critical to a deception jammer. This paper proposes a jamming algorithm based on parallel convolution and one-bit quantization. The algorithm is able to produce a single false target on ISAR image by the jammer itself. The requirement for computation resource is within the capabilities of current digital signal processors such as FPGA or DSP. The method processes the samples of radar signal in parallel and generates the jamming signal at the rate of ADC data, solving the problem that the real-time performance is not satisfied when the input data rate for convolution is far higher than the clock frequency of FPGA. In order to reduce the computation load of convolution, one-bit quantization is utilized. The complex multiplication is implemented by logical resources, which significantly reduces the consumption of FPGA multipliers. The parallel convolution jamming signal, whose date rate exceeds the FPGA clock rate, is introduced and analyzed in detail. In theory, the bandwidth of jamming signal can be half of the sampling frequency of high speed ADC, making the proposed jamming algorithm able to counter ultra-wideband ISAR signals. The performance and validity of the proposed method are verified by simulations. This jamming method is real-time and capable of producing a false target of large size at the low cost of FPGA device.

URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2019EBP3109/_p

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@ARTICLE{e103-b_5_609,

author={Ning TAI, Huan LIN, Chao WEI, Yongwei LU, Chao WANG, Kaibo CUI, },

journal={IEICE TRANSACTIONS on Communications},

title={A Wideband Real-Time Deception Jamming Method for Countering ISAR Based on Parallel Convolution},

year={2020},

volume={E103-B},

number={5},

pages={609-617},

abstract={Since ISAR is widely applied in many occasions and provides high resolution images of the target, ISAR countermeasures are attracting more and more attention. Most of the present methods of deception jamming are not suitable for engineering realization due to the heavy computation load or the large calculation delay. Deception jamming against ISAR requires large computation resource and real-time performance algorithms. Many studies on false target jamming assume that the jammer is able to receive the target echo or transmit the jamming signal to the real target, which is sometimes not possible. How to impose the target property onto the intercepted radar signal is critical to a deception jammer. This paper proposes a jamming algorithm based on parallel convolution and one-bit quantization. The algorithm is able to produce a single false target on ISAR image by the jammer itself. The requirement for computation resource is within the capabilities of current digital signal processors such as FPGA or DSP. The method processes the samples of radar signal in parallel and generates the jamming signal at the rate of ADC data, solving the problem that the real-time performance is not satisfied when the input data rate for convolution is far higher than the clock frequency of FPGA. In order to reduce the computation load of convolution, one-bit quantization is utilized. The complex multiplication is implemented by logical resources, which significantly reduces the consumption of FPGA multipliers. The parallel convolution jamming signal, whose date rate exceeds the FPGA clock rate, is introduced and analyzed in detail. In theory, the bandwidth of jamming signal can be half of the sampling frequency of high speed ADC, making the proposed jamming algorithm able to counter ultra-wideband ISAR signals. The performance and validity of the proposed method are verified by simulations. This jamming method is real-time and capable of producing a false target of large size at the low cost of FPGA device.},

keywords={},

doi={10.1587/transcom.2019EBP3109},

ISSN={1745-1345},

month={May},}

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TY - JOUR

TI - A Wideband Real-Time Deception Jamming Method for Countering ISAR Based on Parallel Convolution

T2 - IEICE TRANSACTIONS on Communications

SP - 609

EP - 617

AU - Ning TAI

AU - Huan LIN

AU - Chao WEI

AU - Yongwei LU

AU - Chao WANG

AU - Kaibo CUI

PY - 2020

DO - 10.1587/transcom.2019EBP3109

JO - IEICE TRANSACTIONS on Communications

SN - 1745-1345

VL - E103-B

IS - 5

JA - IEICE TRANSACTIONS on Communications

Y1 - May 2020

AB - Since ISAR is widely applied in many occasions and provides high resolution images of the target, ISAR countermeasures are attracting more and more attention. Most of the present methods of deception jamming are not suitable for engineering realization due to the heavy computation load or the large calculation delay. Deception jamming against ISAR requires large computation resource and real-time performance algorithms. Many studies on false target jamming assume that the jammer is able to receive the target echo or transmit the jamming signal to the real target, which is sometimes not possible. How to impose the target property onto the intercepted radar signal is critical to a deception jammer. This paper proposes a jamming algorithm based on parallel convolution and one-bit quantization. The algorithm is able to produce a single false target on ISAR image by the jammer itself. The requirement for computation resource is within the capabilities of current digital signal processors such as FPGA or DSP. The method processes the samples of radar signal in parallel and generates the jamming signal at the rate of ADC data, solving the problem that the real-time performance is not satisfied when the input data rate for convolution is far higher than the clock frequency of FPGA. In order to reduce the computation load of convolution, one-bit quantization is utilized. The complex multiplication is implemented by logical resources, which significantly reduces the consumption of FPGA multipliers. The parallel convolution jamming signal, whose date rate exceeds the FPGA clock rate, is introduced and analyzed in detail. In theory, the bandwidth of jamming signal can be half of the sampling frequency of high speed ADC, making the proposed jamming algorithm able to counter ultra-wideband ISAR signals. The performance and validity of the proposed method are verified by simulations. This jamming method is real-time and capable of producing a false target of large size at the low cost of FPGA device.

ER -