IEICE TRANSACTIONS on Communications
Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder
Summary :
In order to reduce the iterative decoding delay of convolutional turbo codes, this paper presents a concurrent decoding algorithm for the hardware implementation of turbo convolutional decoders. Different than a general turbo code, the hardware turbo decoder based on the proposed algorithm can update the priori information of message for each component code in a bit-by-bit manner as soon as it is generated by the other component code. The two component codes in a turbo code can thus be decoded concurrently, by using a single MAP decoder, subsequently reducing the decoding latency by approximately half while maintaining the bit error rate performance and a comparable hardware complexity, as a general turbo decoder.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E93-B No.1 pp.1-8
- Publication Date
- 2010/01/01
- Publicized
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.E93.B.1
- Type of Manuscript
- PAPER
- Category
- Fundamental Theories for Communications
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Ya-Cheng LU, Erl-Huei LU, "Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder" in IEICE TRANSACTIONS on Communications,
vol. E93-B, no. 1, pp. 1-8, January 2010, doi: 10.1587/transcom.E93.B.1.
Abstract: In order to reduce the iterative decoding delay of convolutional turbo codes, this paper presents a concurrent decoding algorithm for the hardware implementation of turbo convolutional decoders. Different than a general turbo code, the hardware turbo decoder based on the proposed algorithm can update the priori information of message for each component code in a bit-by-bit manner as soon as it is generated by the other component code. The two component codes in a turbo code can thus be decoded concurrently, by using a single MAP decoder, subsequently reducing the decoding latency by approximately half while maintaining the bit error rate performance and a comparable hardware complexity, as a general turbo decoder.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E93.B.1/_p
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@ARTICLE{e93-b_1_1,
author={Ya-Cheng LU, Erl-Huei LU, },
journal={IEICE TRANSACTIONS on Communications},
title={Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder},
year={2010},
volume={E93-B},
number={1},
pages={1-8},
abstract={In order to reduce the iterative decoding delay of convolutional turbo codes, this paper presents a concurrent decoding algorithm for the hardware implementation of turbo convolutional decoders. Different than a general turbo code, the hardware turbo decoder based on the proposed algorithm can update the priori information of message for each component code in a bit-by-bit manner as soon as it is generated by the other component code. The two component codes in a turbo code can thus be decoded concurrently, by using a single MAP decoder, subsequently reducing the decoding latency by approximately half while maintaining the bit error rate performance and a comparable hardware complexity, as a general turbo decoder.},
keywords={},
doi={10.1587/transcom.E93.B.1},
ISSN={1745-1345},
month={January},}
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TY - JOUR
TI - Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder
T2 - IEICE TRANSACTIONS on Communications
SP - 1
EP - 8
AU - Ya-Cheng LU
AU - Erl-Huei LU
PY - 2010
DO - 10.1587/transcom.E93.B.1
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E93-B
IS - 1
JA - IEICE TRANSACTIONS on Communications
Y1 - January 2010
AB - In order to reduce the iterative decoding delay of convolutional turbo codes, this paper presents a concurrent decoding algorithm for the hardware implementation of turbo convolutional decoders. Different than a general turbo code, the hardware turbo decoder based on the proposed algorithm can update the priori information of message for each component code in a bit-by-bit manner as soon as it is generated by the other component code. The two component codes in a turbo code can thus be decoded concurrently, by using a single MAP decoder, subsequently reducing the decoding latency by approximately half while maintaining the bit error rate performance and a comparable hardware complexity, as a general turbo decoder.
ER -
English
