A Compact Design of a Low Frequency Quadrature DDFS with Low Distortion Using Analog Shapers
Summary :
An analysis and design of a CMOS differential pair and a common source amplifier for shaping a triangular signal into 0-π/4 segments of sine and cosine waveforms are presented. By multiplexing these two shaped outputs, low distortion full sine and cosine signals can be produced at one fourth the frequency of the triangular input. These two circuits can be combined with one DAC and a phase accumulator to form a compact quadrature direct digital frequency synthesizer (Q-DDFS) suitable for generating low distortion sinusoidal signals at low frequency. The shapers are biased by two current generators specially designed to compensate for process parameter variations. MOS dimensional mismatch is also studied. The analog part of the Q-DDFS is synthesized using 0.18-micron n-well CMOS technology. A simulation shows that the circuit consumes 1.3 mW and can generate 19.96 mV 50 kHz sine and cosine signals with spurious free dynamic range (SFDR) of around 50 dBc from a Q-DDFS running at 1.6 MHz.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E94-B No.9 pp.2574-2581
- Publication Date
- 2011/09/01
- Publicized
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.E94.B.2574
- Type of Manuscript
- PAPER
- Category
- Wireless Communication Technologies
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Keyword
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Kanitpong PENGWON, Ekachai LEELARASMEE, "A Compact Design of a Low Frequency Quadrature DDFS with Low Distortion Using Analog Shapers" in IEICE TRANSACTIONS on Communications,
vol. E94-B, no. 9, pp. 2574-2581, September 2011, doi: 10.1587/transcom.E94.B.2574.
Abstract: An analysis and design of a CMOS differential pair and a common source amplifier for shaping a triangular signal into 0-π/4 segments of sine and cosine waveforms are presented. By multiplexing these two shaped outputs, low distortion full sine and cosine signals can be produced at one fourth the frequency of the triangular input. These two circuits can be combined with one DAC and a phase accumulator to form a compact quadrature direct digital frequency synthesizer (Q-DDFS) suitable for generating low distortion sinusoidal signals at low frequency. The shapers are biased by two current generators specially designed to compensate for process parameter variations. MOS dimensional mismatch is also studied. The analog part of the Q-DDFS is synthesized using 0.18-micron n-well CMOS technology. A simulation shows that the circuit consumes 1.3 mW and can generate 19.96 mV 50 kHz sine and cosine signals with spurious free dynamic range (SFDR) of around 50 dBc from a Q-DDFS running at 1.6 MHz.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E94.B.2574/_p
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@ARTICLE{e94-b_9_2574,
author={Kanitpong PENGWON, Ekachai LEELARASMEE, },
journal={IEICE TRANSACTIONS on Communications},
title={A Compact Design of a Low Frequency Quadrature DDFS with Low Distortion Using Analog Shapers},
year={2011},
volume={E94-B},
number={9},
pages={2574-2581},
abstract={An analysis and design of a CMOS differential pair and a common source amplifier for shaping a triangular signal into 0-π/4 segments of sine and cosine waveforms are presented. By multiplexing these two shaped outputs, low distortion full sine and cosine signals can be produced at one fourth the frequency of the triangular input. These two circuits can be combined with one DAC and a phase accumulator to form a compact quadrature direct digital frequency synthesizer (Q-DDFS) suitable for generating low distortion sinusoidal signals at low frequency. The shapers are biased by two current generators specially designed to compensate for process parameter variations. MOS dimensional mismatch is also studied. The analog part of the Q-DDFS is synthesized using 0.18-micron n-well CMOS technology. A simulation shows that the circuit consumes 1.3 mW and can generate 19.96 mV 50 kHz sine and cosine signals with spurious free dynamic range (SFDR) of around 50 dBc from a Q-DDFS running at 1.6 MHz.},
keywords={},
doi={10.1587/transcom.E94.B.2574},
ISSN={1745-1345},
month={September},}
Copy
TY - JOUR
TI - A Compact Design of a Low Frequency Quadrature DDFS with Low Distortion Using Analog Shapers
T2 - IEICE TRANSACTIONS on Communications
SP - 2574
EP - 2581
AU - Kanitpong PENGWON
AU - Ekachai LEELARASMEE
PY - 2011
DO - 10.1587/transcom.E94.B.2574
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E94-B
IS - 9
JA - IEICE TRANSACTIONS on Communications
Y1 - September 2011
AB - An analysis and design of a CMOS differential pair and a common source amplifier for shaping a triangular signal into 0-π/4 segments of sine and cosine waveforms are presented. By multiplexing these two shaped outputs, low distortion full sine and cosine signals can be produced at one fourth the frequency of the triangular input. These two circuits can be combined with one DAC and a phase accumulator to form a compact quadrature direct digital frequency synthesizer (Q-DDFS) suitable for generating low distortion sinusoidal signals at low frequency. The shapers are biased by two current generators specially designed to compensate for process parameter variations. MOS dimensional mismatch is also studied. The analog part of the Q-DDFS is synthesized using 0.18-micron n-well CMOS technology. A simulation shows that the circuit consumes 1.3 mW and can generate 19.96 mV 50 kHz sine and cosine signals with spurious free dynamic range (SFDR) of around 50 dBc from a Q-DDFS running at 1.6 MHz.
ER -
English
