A Parity Checker for a Large RNS Numbers Based on Montgomery Reduction Method

Taek-Won KWON; Jun-Rim CHOI

doi:10.1093/ietele/e88-c.9.1880

A Parity Checker for a Large RNS Numbers Based on Montgomery Reduction Method

Taek-Won KWON, Jun-Rim CHOI

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Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2^r-(2^l1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.

Publication: IEICE TRANSACTIONS on Electronics Vol.E88-C No.9 pp.1880-1885

Publication Date: 2005/09/01

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DOI: 10.1093/ietele/e88-c.9.1880

Type of Manuscript: PAPER

Category: Electronic Circuits

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Taek-Won KWON, Jun-Rim CHOI, "A Parity Checker for a Large RNS Numbers Based on Montgomery Reduction Method" in IEICE TRANSACTIONS on Electronics, vol. E88-C, no. 9, pp. 1880-1885, September 2005, doi: 10.1093/ietele/e88-c.9.1880.
Abstract: Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2^r-(2^l1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.9.1880/_p

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@ARTICLE{e88-c_9_1880,
author={Taek-Won KWON, Jun-Rim CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Parity Checker for a Large RNS Numbers Based on Montgomery Reduction Method},
year={2005},
volume={E88-C},
number={9},
pages={1880-1885},
abstract={Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2^r-(2^l1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.},
keywords={},
doi={10.1093/ietele/e88-c.9.1880},
ISSN={},
month={September},}

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TY - JOUR
TI - A Parity Checker for a Large RNS Numbers Based on Montgomery Reduction Method
T2 - IEICE TRANSACTIONS on Electronics
SP - 1880
EP - 1885
AU - Taek-Won KWON
AU - Jun-Rim CHOI
PY - 2005
DO - 10.1093/ietele/e88-c.9.1880
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2005
AB - Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2^r-(2^l1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.
ER -