IEICE TRANSACTIONS on Electronics
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
Summary :
For super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 µW for QCIF 15-fps in a 130-nm technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1629-1636
- Publication Date
- 2006/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.11.1629
- Type of Manuscript
- Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
- Category
Authors
Keyword
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Junichi MIYAKOSHI, Yuichiro MURACHI, Tomokazu ISHIHARA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 11, pp. 1629-1636, November 2006, doi: 10.1093/ietele/e89-c.11.1629.
Abstract: For super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 µW for QCIF 15-fps in a 130-nm technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1629/_p
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@ARTICLE{e89-c_11_1629,
author={Junichi MIYAKOSHI, Yuichiro MURACHI, Tomokazu ISHIHARA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing},
year={2006},
volume={E89-C},
number={11},
pages={1629-1636},
abstract={For super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 µW for QCIF 15-fps in a 130-nm technology.},
keywords={},
doi={10.1093/ietele/e89-c.11.1629},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
T2 - IEICE TRANSACTIONS on Electronics
SP - 1629
EP - 1636
AU - Junichi MIYAKOSHI
AU - Yuichiro MURACHI
AU - Tomokazu ISHIHARA
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2006
DO - 10.1093/ietele/e89-c.11.1629
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - For super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 µW for QCIF 15-fps in a 130-nm technology.
ER -
English
