In this paper, we report a new collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between extrinsic emitter and subemitter for current confinement. A theoretical study is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. The structural parameters of the device and bias conditions on the buried layer are investigated to understand the limitations and the potential of devices. It is found that the emitter structure should be optimized to achieve the high efficiency of current confinement and the design of overlap between base-collector junction and buried layer is effective to suppress the carrier-blocking effect. Moreover, proposed C-up HBT demonstrates the similar current-gain cutoff frequency (fT) characteristics compared with conventional C-up HBT fabricated by ion implantations. The impact of fT caused by the external base-emitter capacitance (CBE,ext) can be relieved by further structural optimization of the emitter layer and lateral scaling of the extrinsic region. To clarify the feasibility of the proposed C-up HBTs, we also specify the fabrication process for the devices with epitaxial regrowth techniques.
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Hung-tsao HSU, Yue-ming HSIN, "Simulation Study of a Novel Collector-up npn InGaP/GaAs Heterojunction Bipolar Transistor with a p-Type Doping Buried Layer for Current Confinement" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 1, pp. 171-178, January 2007, doi: 10.1093/ietele/e90-c.1.171.
Abstract: In this paper, we report a new collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between extrinsic emitter and subemitter for current confinement. A theoretical study is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. The structural parameters of the device and bias conditions on the buried layer are investigated to understand the limitations and the potential of devices. It is found that the emitter structure should be optimized to achieve the high efficiency of current confinement and the design of overlap between base-collector junction and buried layer is effective to suppress the carrier-blocking effect. Moreover, proposed C-up HBT demonstrates the similar current-gain cutoff frequency (fT) characteristics compared with conventional C-up HBT fabricated by ion implantations. The impact of fT caused by the external base-emitter capacitance (CBE,ext) can be relieved by further structural optimization of the emitter layer and lateral scaling of the extrinsic region. To clarify the feasibility of the proposed C-up HBTs, we also specify the fabrication process for the devices with epitaxial regrowth techniques.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.1.171/_p
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@ARTICLE{e90-c_1_171,
author={Hung-tsao HSU, Yue-ming HSIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Simulation Study of a Novel Collector-up npn InGaP/GaAs Heterojunction Bipolar Transistor with a p-Type Doping Buried Layer for Current Confinement},
year={2007},
volume={E90-C},
number={1},
pages={171-178},
abstract={In this paper, we report a new collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between extrinsic emitter and subemitter for current confinement. A theoretical study is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. The structural parameters of the device and bias conditions on the buried layer are investigated to understand the limitations and the potential of devices. It is found that the emitter structure should be optimized to achieve the high efficiency of current confinement and the design of overlap between base-collector junction and buried layer is effective to suppress the carrier-blocking effect. Moreover, proposed C-up HBT demonstrates the similar current-gain cutoff frequency (fT) characteristics compared with conventional C-up HBT fabricated by ion implantations. The impact of fT caused by the external base-emitter capacitance (CBE,ext) can be relieved by further structural optimization of the emitter layer and lateral scaling of the extrinsic region. To clarify the feasibility of the proposed C-up HBTs, we also specify the fabrication process for the devices with epitaxial regrowth techniques.},
keywords={},
doi={10.1093/ietele/e90-c.1.171},
ISSN={1745-1353},
month={January},}
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TY - JOUR
TI - Simulation Study of a Novel Collector-up npn InGaP/GaAs Heterojunction Bipolar Transistor with a p-Type Doping Buried Layer for Current Confinement
T2 - IEICE TRANSACTIONS on Electronics
SP - 171
EP - 178
AU - Hung-tsao HSU
AU - Yue-ming HSIN
PY - 2007
DO - 10.1093/ietele/e90-c.1.171
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2007
AB - In this paper, we report a new collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between extrinsic emitter and subemitter for current confinement. A theoretical study is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. The structural parameters of the device and bias conditions on the buried layer are investigated to understand the limitations and the potential of devices. It is found that the emitter structure should be optimized to achieve the high efficiency of current confinement and the design of overlap between base-collector junction and buried layer is effective to suppress the carrier-blocking effect. Moreover, proposed C-up HBT demonstrates the similar current-gain cutoff frequency (fT) characteristics compared with conventional C-up HBT fabricated by ion implantations. The impact of fT caused by the external base-emitter capacitance (CBE,ext) can be relieved by further structural optimization of the emitter layer and lateral scaling of the extrinsic region. To clarify the feasibility of the proposed C-up HBTs, we also specify the fabrication process for the devices with epitaxial regrowth techniques.
ER -