IEICE TRANSACTIONS on Electronics
A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation
Summary :
In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.1 pp.196-200
- Publication Date
- 2007/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.1.196
- Type of Manuscript
- LETTER
- Category
- Electronic Circuits
Authors
Keyword
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Ching-Yuan YANG, Jung-Mao LIN, "A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 1, pp. 196-200, January 2007, doi: 10.1093/ietele/e90-c.1.196.
Abstract: In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.1.196/_p
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@ARTICLE{e90-c_1_196,
author={Ching-Yuan YANG, Jung-Mao LIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation},
year={2007},
volume={E90-C},
number={1},
pages={196-200},
abstract={In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4
keywords={},
doi={10.1093/ietele/e90-c.1.196},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation
T2 - IEICE TRANSACTIONS on Electronics
SP - 196
EP - 200
AU - Ching-Yuan YANG
AU - Jung-Mao LIN
PY - 2007
DO - 10.1093/ietele/e90-c.1.196
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2007
AB - In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4
ER -
English
