IEICE TRANSACTIONS on Electronics
Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms
Summary :
In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 µm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.1964-1971
- Publication Date
- 2007/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.10.1964
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
- Category
- VLSI Architecture for Communication/Server Systems
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Qi WANG, Kazunori SHIMIZU, Takeshi IKENAGA, Satoshi GOTO, "Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 10, pp. 1964-1971, October 2007, doi: 10.1093/ietele/e90-c.10.1964.
Abstract: In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 µm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.10.1964/_p
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@ARTICLE{e90-c_10_1964,
author={Qi WANG, Kazunori SHIMIZU, Takeshi IKENAGA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms},
year={2007},
volume={E90-C},
number={10},
pages={1964-1971},
abstract={In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 µm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.},
keywords={},
doi={10.1093/ietele/e90-c.10.1964},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms
T2 - IEICE TRANSACTIONS on Electronics
SP - 1964
EP - 1971
AU - Qi WANG
AU - Kazunori SHIMIZU
AU - Takeshi IKENAGA
AU - Satoshi GOTO
PY - 2007
DO - 10.1093/ietele/e90-c.10.1964
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2007
AB - In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 µm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.
ER -
English
