IEICE TRANSACTIONS on Electronics
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits
Summary :
A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.12 pp.2278-2284
- Publication Date
- 2007/12/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.12.2278
- Type of Manuscript
- PAPER
- Category
- Superconducting Electronics
Authors
Keyword
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Koji OBATA, Kazuyoshi TAKAGI, Naofumi TAKAGI, "A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 12, pp. 2278-2284, December 2007, doi: 10.1093/ietele/e90-c.12.2278.
Abstract: A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.12.2278/_p
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@ARTICLE{e90-c_12_2278,
author={Koji OBATA, Kazuyoshi TAKAGI, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits},
year={2007},
volume={E90-C},
number={12},
pages={2278-2284},
abstract={A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.},
keywords={},
doi={10.1093/ietele/e90-c.12.2278},
ISSN={1745-1353},
month={December},}
Copy
TY - JOUR
TI - A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 2278
EP - 2284
AU - Koji OBATA
AU - Kazuyoshi TAKAGI
AU - Naofumi TAKAGI
PY - 2007
DO - 10.1093/ietele/e90-c.12.2278
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2007
AB - A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.
ER -
English
