IEICE TRANSACTIONS on Electronics
A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core
Summary :
We have developed a hardware accelerator for Java platforms, integrated on a SuperH microprocessor core, using a 130-nm CMOS process. The Java accelerator, a bytecode translation unit (BTU), is tightly coupled with the CPU to share resources. The BTU supports 159 basic bytecodes and 5 or 6 optional bytecodes. It supports both connected device configuration (CDC) 1.0 and connected limited device configuration (CLDC) 1.0.4 technologies. The BTU corresponds to the dual-issued superscalar CPU and applies a new method, control-sharing. With this method, the BTU always grasps the pipeline status of the CPU, and the Java program is processed by both the BTU and the CPU. To implement this method, we developed some acceleration techniques: fast branch requests, enhanced CPU instructions, Java runtime exception detection hardware, and fewer overhead cycles of handover between the BTU and the CPU. In particular, the BTU can detect Java runtime exceptions in parallel with other processing, such as an array access. With previous methods, there is a disadvantage in that CPU efficiency decreases for Java-specific processing, such as array index bounds checking. The sample chip was fabricated in Renesas 130-nm, five-layer Cu, dual-vth low-power CMOS technology. The chip runs at 216 MHz and 1.2 V. The BTU has 75 kG. The benchmark on an evaluation board showed 6.55 embedded caffeine marks (ECM)/MHz on the CLDC 1.0.4 configuration, a tenfold speed increase without the BTU for roughly the same power consumption. In other words, power savings of 90 percent with the same performance were achieved.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.2 pp.523-530
- Publication Date
- 2007/02/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.2.523
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Tetsuya YAMADA
Naohiko IRIE
Takanobu TSUNODA
Takahiro IRITA
Kenji KITAGAWA
Ryohei YOSHIDA
Keisuke TOYAMA
Motoaki SATOYAMA
Keyword
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Tetsuya YAMADA, Naohiko IRIE, Takanobu TSUNODA, Takahiro IRITA, Kenji KITAGAWA, Ryohei YOSHIDA, Keisuke TOYAMA, Motoaki SATOYAMA, "A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 2, pp. 523-530, February 2007, doi: 10.1093/ietele/e90-c.2.523.
Abstract: We have developed a hardware accelerator for Java platforms, integrated on a SuperH microprocessor core, using a 130-nm CMOS process. The Java accelerator, a bytecode translation unit (BTU), is tightly coupled with the CPU to share resources. The BTU supports 159 basic bytecodes and 5 or 6 optional bytecodes. It supports both connected device configuration (CDC) 1.0 and connected limited device configuration (CLDC) 1.0.4 technologies. The BTU corresponds to the dual-issued superscalar CPU and applies a new method, control-sharing. With this method, the BTU always grasps the pipeline status of the CPU, and the Java program is processed by both the BTU and the CPU. To implement this method, we developed some acceleration techniques: fast branch requests, enhanced CPU instructions, Java runtime exception detection hardware, and fewer overhead cycles of handover between the BTU and the CPU. In particular, the BTU can detect Java runtime exceptions in parallel with other processing, such as an array access. With previous methods, there is a disadvantage in that CPU efficiency decreases for Java-specific processing, such as array index bounds checking. The sample chip was fabricated in Renesas 130-nm, five-layer Cu, dual-vth low-power CMOS technology. The chip runs at 216 MHz and 1.2 V. The BTU has 75 kG. The benchmark on an evaluation board showed 6.55 embedded caffeine marks (ECM)/MHz on the CLDC 1.0.4 configuration, a tenfold speed increase without the BTU for roughly the same power consumption. In other words, power savings of 90 percent with the same performance were achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.2.523/_p
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@ARTICLE{e90-c_2_523,
author={Tetsuya YAMADA, Naohiko IRIE, Takanobu TSUNODA, Takahiro IRITA, Kenji KITAGAWA, Ryohei YOSHIDA, Keisuke TOYAMA, Motoaki SATOYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core},
year={2007},
volume={E90-C},
number={2},
pages={523-530},
abstract={We have developed a hardware accelerator for Java platforms, integrated on a SuperH microprocessor core, using a 130-nm CMOS process. The Java accelerator, a bytecode translation unit (BTU), is tightly coupled with the CPU to share resources. The BTU supports 159 basic bytecodes and 5 or 6 optional bytecodes. It supports both connected device configuration (CDC) 1.0 and connected limited device configuration (CLDC) 1.0.4 technologies. The BTU corresponds to the dual-issued superscalar CPU and applies a new method, control-sharing. With this method, the BTU always grasps the pipeline status of the CPU, and the Java program is processed by both the BTU and the CPU. To implement this method, we developed some acceleration techniques: fast branch requests, enhanced CPU instructions, Java runtime exception detection hardware, and fewer overhead cycles of handover between the BTU and the CPU. In particular, the BTU can detect Java runtime exceptions in parallel with other processing, such as an array access. With previous methods, there is a disadvantage in that CPU efficiency decreases for Java-specific processing, such as array index bounds checking. The sample chip was fabricated in Renesas 130-nm, five-layer Cu, dual-vth low-power CMOS technology. The chip runs at 216 MHz and 1.2 V. The BTU has 75 kG. The benchmark on an evaluation board showed 6.55 embedded caffeine marks (ECM)/MHz on the CLDC 1.0.4 configuration, a tenfold speed increase without the BTU for roughly the same power consumption. In other words, power savings of 90 percent with the same performance were achieved.},
keywords={},
doi={10.1093/ietele/e90-c.2.523},
ISSN={1745-1353},
month={February},}
Copy
TY - JOUR
TI - A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core
T2 - IEICE TRANSACTIONS on Electronics
SP - 523
EP - 530
AU - Tetsuya YAMADA
AU - Naohiko IRIE
AU - Takanobu TSUNODA
AU - Takahiro IRITA
AU - Kenji KITAGAWA
AU - Ryohei YOSHIDA
AU - Keisuke TOYAMA
AU - Motoaki SATOYAMA
PY - 2007
DO - 10.1093/ietele/e90-c.2.523
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2007
AB - We have developed a hardware accelerator for Java platforms, integrated on a SuperH microprocessor core, using a 130-nm CMOS process. The Java accelerator, a bytecode translation unit (BTU), is tightly coupled with the CPU to share resources. The BTU supports 159 basic bytecodes and 5 or 6 optional bytecodes. It supports both connected device configuration (CDC) 1.0 and connected limited device configuration (CLDC) 1.0.4 technologies. The BTU corresponds to the dual-issued superscalar CPU and applies a new method, control-sharing. With this method, the BTU always grasps the pipeline status of the CPU, and the Java program is processed by both the BTU and the CPU. To implement this method, we developed some acceleration techniques: fast branch requests, enhanced CPU instructions, Java runtime exception detection hardware, and fewer overhead cycles of handover between the BTU and the CPU. In particular, the BTU can detect Java runtime exceptions in parallel with other processing, such as an array access. With previous methods, there is a disadvantage in that CPU efficiency decreases for Java-specific processing, such as array index bounds checking. The sample chip was fabricated in Renesas 130-nm, five-layer Cu, dual-vth low-power CMOS technology. The chip runs at 216 MHz and 1.2 V. The BTU has 75 kG. The benchmark on an evaluation board showed 6.55 embedded caffeine marks (ECM)/MHz on the CLDC 1.0.4 configuration, a tenfold speed increase without the BTU for roughly the same power consumption. In other words, power savings of 90 percent with the same performance were achieved.
ER -
English
