Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices
Summary :
Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (Lg) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.842-847
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.842
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
- Device
Authors
Keyword
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Katsuhiko TANAKA, Kiyoshi TAKEUCHI, Masami HANE, "Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 842-847, April 2007, doi: 10.1093/ietele/e90-c.4.842.
Abstract: Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (Lg) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.842/_p
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@ARTICLE{e90-c_4_842,
author={Katsuhiko TANAKA, Kiyoshi TAKEUCHI, Masami HANE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices},
year={2007},
volume={E90-C},
number={4},
pages={842-847},
abstract={Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (Lg) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.},
keywords={},
doi={10.1093/ietele/e90-c.4.842},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 842
EP - 847
AU - Katsuhiko TANAKA
AU - Kiyoshi TAKEUCHI
AU - Masami HANE
PY - 2007
DO - 10.1093/ietele/e90-c.4.842
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (Lg) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.
ER -
English
