Power and Skew Aware Point Diffusion Clock Network
Summary :
This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.11 pp.1832-1834
- Publication Date
- 2008/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.11.1832
- Type of Manuscript
- LETTER
- Category
- Integrated Electronics
Authors
Keyword
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Gunok JUNG, Chunghee KIM, Kyoungkuk CHAE, Giho PARK, Sung Bae PARK, "Power and Skew Aware Point Diffusion Clock Network" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 11, pp. 1832-1834, November 2008, doi: 10.1093/ietele/e91-c.11.1832.
Abstract: This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.11.1832/_p
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@ARTICLE{e91-c_11_1832,
author={Gunok JUNG, Chunghee KIM, Kyoungkuk CHAE, Giho PARK, Sung Bae PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power and Skew Aware Point Diffusion Clock Network},
year={2008},
volume={E91-C},
number={11},
pages={1832-1834},
abstract={This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.},
keywords={},
doi={10.1093/ietele/e91-c.11.1832},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - Power and Skew Aware Point Diffusion Clock Network
T2 - IEICE TRANSACTIONS on Electronics
SP - 1832
EP - 1834
AU - Gunok JUNG
AU - Chunghee KIM
AU - Kyoungkuk CHAE
AU - Giho PARK
AU - Sung Bae PARK
PY - 2008
DO - 10.1093/ietele/e91-c.11.1832
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2008
AB - This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.
ER -
English
