IEICE TRANSACTIONS on Electronics
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
Summary :
This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 µm CMOS technology. The processing time is 83.2 µs@100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.479-486
- Publication Date
- 2008/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.4.479
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
- Category
Authors
Keyword
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Masanori HARIYAMA, Naoto YOKOYAMA, Michitaka KAMEYAMA, "Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 4, pp. 479-486, April 2008, doi: 10.1093/ietele/e91-c.4.479.
Abstract: This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 µm CMOS technology. The processing time is 83.2 µs@100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.479/_p
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@ARTICLE{e91-c_4_479,
author={Masanori HARIYAMA, Naoto YOKOYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling},
year={2008},
volume={E91-C},
number={4},
pages={479-486},
abstract={This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 µm CMOS technology. The processing time is 83.2 µs@100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.},
keywords={},
doi={10.1093/ietele/e91-c.4.479},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
T2 - IEICE TRANSACTIONS on Electronics
SP - 479
EP - 486
AU - Masanori HARIYAMA
AU - Naoto YOKOYAMA
AU - Michitaka KAMEYAMA
PY - 2008
DO - 10.1093/ietele/e91-c.4.479
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 µm CMOS technology. The processing time is 83.2 µs@100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.
ER -
English
