Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems

Nicola E. L'INSALATA; Sergio SAPONARA; Luca FANUCCI; Pierangelo TERRENI

doi:10.1093/ietele/e91-c.4.487

Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems

Nicola E. L'INSALATA, Sergio SAPONARA, Luca FANUCCI, Pierangelo TERRENI

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This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.487-496

Publication Date: 2008/04/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.4.487

Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)

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Nicola E. L'INSALATA, Sergio SAPONARA, Luca FANUCCI, Pierangelo TERRENI, "Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 4, pp. 487-496, April 2008, doi: 10.1093/ietele/e91-c.4.487.
Abstract: This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.487/_p

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@ARTICLE{e91-c_4_487,
author={Nicola E. L'INSALATA, Sergio SAPONARA, Luca FANUCCI, Pierangelo TERRENI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems},
year={2008},
volume={E91-C},
number={4},
pages={487-496},
abstract={This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.},
keywords={},
doi={10.1093/ietele/e91-c.4.487},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 487
EP - 496
AU - Nicola E. L'INSALATA
AU - Sergio SAPONARA
AU - Luca FANUCCI
AU - Pierangelo TERRENI
PY - 2008
DO - 10.1093/ietele/e91-c.4.487
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.
ER -