An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

Nobuo KARAKI; Takashi NANMOTO; Satoshi INOUE

doi:10.1093/ietele/e91-c.5.721

An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

Nobuo KARAKI, Takashi NANMOTO, Satoshi INOUE

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This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA^®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL^® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500 kHz, drawing 180 µA from a 5 V power source. The microprocessor's electromagnetic emissions are 21 dB less than those of the synchronous counterpart.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.5 pp.721-730

Publication Date: 2008/05/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.5.721

Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)

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Nobuo KARAKI, Takashi NANMOTO, Satoshi INOUE, "An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 5, pp. 721-730, May 2008, doi: 10.1093/ietele/e91-c.5.721.
Abstract: This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA^®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL^® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500 kHz, drawing 180 µA from a 5 V power source. The microprocessor's electromagnetic emissions are 21 dB less than those of the synchronous counterpart.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.5.721/_p

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@ARTICLE{e91-c_5_721,
author={Nobuo KARAKI, Takashi NANMOTO, Satoshi INOUE, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor},
year={2008},
volume={E91-C},
number={5},
pages={721-730},
abstract={This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA^®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL^® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500 kHz, drawing 180 µA from a 5 V power source. The microprocessor's electromagnetic emissions are 21 dB less than those of the synchronous counterpart.},
keywords={},
doi={10.1093/ietele/e91-c.5.721},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor
T2 - IEICE TRANSACTIONS on Electronics
SP - 721
EP - 730
AU - Nobuo KARAKI
AU - Takashi NANMOTO
AU - Satoshi INOUE
PY - 2008
DO - 10.1093/ietele/e91-c.5.721
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2008
AB - This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA^®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL^® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500 kHz, drawing 180 µA from a 5 V power source. The microprocessor's electromagnetic emissions are 21 dB less than those of the synchronous counterpart.
ER -