IEICE TRANSACTIONS on Electronics
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Summary :
This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.9 pp.1419-1426
- Publication Date
- 2008/09/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.9.1419
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
- Category
Authors
Keyword
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Masanori HARIYAMA, Shota ISHIHARA, Michitaka KAMEYAMA, "Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1419-1426, September 2008, doi: 10.1093/ietele/e91-c.9.1419.
Abstract: This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1419/_p
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@ARTICLE{e91-c_9_1419,
author={Masanori HARIYAMA, Shota ISHIHARA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture},
year={2008},
volume={E91-C},
number={9},
pages={1419-1426},
abstract={This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.},
keywords={},
doi={10.1093/ietele/e91-c.9.1419},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1419
EP - 1426
AU - Masanori HARIYAMA
AU - Shota ISHIHARA
AU - Michitaka KAMEYAMA
PY - 2008
DO - 10.1093/ietele/e91-c.9.1419
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.
ER -
English
