IEICE TRANSACTIONS on Electronics
A High Performance 32-Bit Microcontroller for Realtime Applications
Summary :
A 10-MIPS peak performance single-chip MCU (Micro Controller Unit) core has been developed for real time applications. The following features are implemented to improve cost-effectiveness and the worst interrupt response: (1) large-scale on-chip register with overlapping register windows, (2) the mechanism of receiving exception request with concurrent execution of another instruction, (3) load-store architecture, (4) optimized instruction pipelining, and (5) two 32-bit internal and a 16-bit external buses. It delivers about 5-MIPS average performance in some benchmark programs. The worst overall interrupt response time, which is defined to be the one from receiving an interrupt request to saving the general registers in the invoked interrupt routine, is measured to be 2.38 µs, which is about three fold improvements over a commercial 32-bit MCU. The prototype contains only 15,000 gates, and is cost-effective for 16/32-bit single-chip MCU.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E74-C No.11 pp.3766-3774
- Publication Date
- 1991/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
- Category
- Core and Macrocells
Authors
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Masafumi TAKAHASHI, Yasuo YAMADA, Emi KANEKO, Shinichi YOSHIOKA, Haruyuki TAGO, "A High Performance 32-Bit Microcontroller for Realtime Applications" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 11, pp. 3766-3774, November 1991, doi: .
Abstract: A 10-MIPS peak performance single-chip MCU (Micro Controller Unit) core has been developed for real time applications. The following features are implemented to improve cost-effectiveness and the worst interrupt response: (1) large-scale on-chip register with overlapping register windows, (2) the mechanism of receiving exception request with concurrent execution of another instruction, (3) load-store architecture, (4) optimized instruction pipelining, and (5) two 32-bit internal and a 16-bit external buses. It delivers about 5-MIPS average performance in some benchmark programs. The worst overall interrupt response time, which is defined to be the one from receiving an interrupt request to saving the general registers in the invoked interrupt routine, is measured to be 2.38 µs, which is about three fold improvements over a commercial 32-bit MCU. The prototype contains only 15,000 gates, and is cost-effective for 16/32-bit single-chip MCU.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_11_3766/_p
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@ARTICLE{e74-c_11_3766,
author={Masafumi TAKAHASHI, Yasuo YAMADA, Emi KANEKO, Shinichi YOSHIOKA, Haruyuki TAGO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High Performance 32-Bit Microcontroller for Realtime Applications},
year={1991},
volume={E74-C},
number={11},
pages={3766-3774},
abstract={A 10-MIPS peak performance single-chip MCU (Micro Controller Unit) core has been developed for real time applications. The following features are implemented to improve cost-effectiveness and the worst interrupt response: (1) large-scale on-chip register with overlapping register windows, (2) the mechanism of receiving exception request with concurrent execution of another instruction, (3) load-store architecture, (4) optimized instruction pipelining, and (5) two 32-bit internal and a 16-bit external buses. It delivers about 5-MIPS average performance in some benchmark programs. The worst overall interrupt response time, which is defined to be the one from receiving an interrupt request to saving the general registers in the invoked interrupt routine, is measured to be 2.38 µs, which is about three fold improvements over a commercial 32-bit MCU. The prototype contains only 15,000 gates, and is cost-effective for 16/32-bit single-chip MCU.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A High Performance 32-Bit Microcontroller for Realtime Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 3766
EP - 3774
AU - Masafumi TAKAHASHI
AU - Yasuo YAMADA
AU - Emi KANEKO
AU - Shinichi YOSHIOKA
AU - Haruyuki TAGO
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1991
AB - A 10-MIPS peak performance single-chip MCU (Micro Controller Unit) core has been developed for real time applications. The following features are implemented to improve cost-effectiveness and the worst interrupt response: (1) large-scale on-chip register with overlapping register windows, (2) the mechanism of receiving exception request with concurrent execution of another instruction, (3) load-store architecture, (4) optimized instruction pipelining, and (5) two 32-bit internal and a 16-bit external buses. It delivers about 5-MIPS average performance in some benchmark programs. The worst overall interrupt response time, which is defined to be the one from receiving an interrupt request to saving the general registers in the invoked interrupt routine, is measured to be 2.38 µs, which is about three fold improvements over a commercial 32-bit MCU. The prototype contains only 15,000 gates, and is cost-effective for 16/32-bit single-chip MCU.
ER -
English
