A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit

Takehisa HAYASHI; Toshio DOI; Mikio YAMAGISHI; Kazuo KOIDE; Akira ISHIYAMA; Masataka HIRAMATSU; Akira YAMAGIWA

A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit

Takehisa HAYASHI, Toshio DOI, Mikio YAMAGISHI, Kazuo KOIDE, Akira ISHIYAMA, Masataka HIRAMATSU, Akira YAMAGIWA

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A 64 b CMOS mainframe execution unit macrocell with error detecting circuits is proposed. The conventional techniques to maintain high reliability have been the parity checking and the duplication of the ALU (Arithmetic Logic Unit). However, the required time for generating the parity from the sum output of the ALU has been undesirable for high-speed operation. In order to achieve a short ALU delay time, a parity predicting logic structure is newly adopted. By utilizing this structure, a one-bit-error detecting function is integrated without duplicating the every ALU circuit. A novel CMOS precharged circuit is also developed to shorten the time required to precharge the whole circuit. When the number of circuit stages is reduced, the precharge time as well as the delay time restricts the ALU cycle time. This new circuitry solves the precharging time accumulation problem in the conventional circuits. A 64 b BCD ALU adopting this technology has been designed and fabricated. The parity predict architecture and the high-speed-precharge circuit have been effective in reducing the delay time by 23% and the precharge time by 42%. A 30% faster cycle time has been achieved with a small increase (4%) in ALU area. The execution unit macrocell, which includes the ALU described above, contains 45 k transistors and it's area is 4.3 mm4.1 mm using the 0.8 µm CMOS triple metal layer technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.11 pp.3775-3779

Publication Date: 1991/11/25

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Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)

Category: Core and Macrocells

Authors

Takehisa HAYASHI
Toshio DOI
Mikio YAMAGISHI
Kazuo KOIDE
Akira ISHIYAMA
Masataka HIRAMATSU
Akira YAMAGIWA

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Takehisa HAYASHI, Toshio DOI, Mikio YAMAGISHI, Kazuo KOIDE, Akira ISHIYAMA, Masataka HIRAMATSU, Akira YAMAGIWA, "A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 11, pp. 3775-3779, November 1991, doi: .
Abstract: A 64 b CMOS mainframe execution unit macrocell with error detecting circuits is proposed. The conventional techniques to maintain high reliability have been the parity checking and the duplication of the ALU (Arithmetic Logic Unit). However, the required time for generating the parity from the sum output of the ALU has been undesirable for high-speed operation. In order to achieve a short ALU delay time, a parity predicting logic structure is newly adopted. By utilizing this structure, a one-bit-error detecting function is integrated without duplicating the every ALU circuit. A novel CMOS precharged circuit is also developed to shorten the time required to precharge the whole circuit. When the number of circuit stages is reduced, the precharge time as well as the delay time restricts the ALU cycle time. This new circuitry solves the precharging time accumulation problem in the conventional circuits. A 64 b BCD ALU adopting this technology has been designed and fabricated. The parity predict architecture and the high-speed-precharge circuit have been effective in reducing the delay time by 23% and the precharge time by 42%. A 30% faster cycle time has been achieved with a small increase (4%) in ALU area. The execution unit macrocell, which includes the ALU described above, contains 45 k transistors and it's area is 4.3 mm4.1 mm using the 0.8 µm CMOS triple metal layer technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_11_3775/_p

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@ARTICLE{e74-c_11_3775,
author={Takehisa HAYASHI, Toshio DOI, Mikio YAMAGISHI, Kazuo KOIDE, Akira ISHIYAMA, Masataka HIRAMATSU, Akira YAMAGIWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit},
year={1991},
volume={E74-C},
number={11},
pages={3775-3779},
abstract={A 64 b CMOS mainframe execution unit macrocell with error detecting circuits is proposed. The conventional techniques to maintain high reliability have been the parity checking and the duplication of the ALU (Arithmetic Logic Unit). However, the required time for generating the parity from the sum output of the ALU has been undesirable for high-speed operation. In order to achieve a short ALU delay time, a parity predicting logic structure is newly adopted. By utilizing this structure, a one-bit-error detecting function is integrated without duplicating the every ALU circuit. A novel CMOS precharged circuit is also developed to shorten the time required to precharge the whole circuit. When the number of circuit stages is reduced, the precharge time as well as the delay time restricts the ALU cycle time. This new circuitry solves the precharging time accumulation problem in the conventional circuits. A 64 b BCD ALU adopting this technology has been designed and fabricated. The parity predict architecture and the high-speed-precharge circuit have been effective in reducing the delay time by 23% and the precharge time by 42%. A 30% faster cycle time has been achieved with a small increase (4%) in ALU area. The execution unit macrocell, which includes the ALU described above, contains 45 k transistors and it's area is 4.3 mm4.1 mm using the 0.8 µm CMOS triple metal layer technology.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 3775
EP - 3779
AU - Takehisa HAYASHI
AU - Toshio DOI
AU - Mikio YAMAGISHI
AU - Kazuo KOIDE
AU - Akira ISHIYAMA
AU - Masataka HIRAMATSU
AU - Akira YAMAGIWA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1991
AB - A 64 b CMOS mainframe execution unit macrocell with error detecting circuits is proposed. The conventional techniques to maintain high reliability have been the parity checking and the duplication of the ALU (Arithmetic Logic Unit). However, the required time for generating the parity from the sum output of the ALU has been undesirable for high-speed operation. In order to achieve a short ALU delay time, a parity predicting logic structure is newly adopted. By utilizing this structure, a one-bit-error detecting function is integrated without duplicating the every ALU circuit. A novel CMOS precharged circuit is also developed to shorten the time required to precharge the whole circuit. When the number of circuit stages is reduced, the precharge time as well as the delay time restricts the ALU cycle time. This new circuitry solves the precharging time accumulation problem in the conventional circuits. A 64 b BCD ALU adopting this technology has been designed and fabricated. The parity predict architecture and the high-speed-precharge circuit have been effective in reducing the delay time by 23% and the precharge time by 42%. A 30% faster cycle time has been achieved with a small increase (4%) in ALU area. The execution unit macrocell, which includes the ALU described above, contains 45 k transistors and it's area is 4.3 mm4.1 mm using the 0.8 µm CMOS triple metal layer technology.
ER -