Performance Evaluation of a Translation Look-Aside Buffer for Highly Integrated Microprocessors
Summary :
This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.10 pp.1202-1211
- Publication Date
- 1992/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Microprocessors)
- Category
- RISC Technologies
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Norio UTSUMI, Akifumi NAGAO, Tetsuro YOSHIMOTO, Ryuichi YAMAGUCHI, Jiro MIYAKE, Hisakazu EDAMATSU, "Performance Evaluation of a Translation Look-Aside Buffer for Highly Integrated Microprocessors" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 10, pp. 1202-1211, October 1992, doi: .
Abstract: This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_10_1202/_p
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@ARTICLE{e75-c_10_1202,
author={Norio UTSUMI, Akifumi NAGAO, Tetsuro YOSHIMOTO, Ryuichi YAMAGUCHI, Jiro MIYAKE, Hisakazu EDAMATSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Performance Evaluation of a Translation Look-Aside Buffer for Highly Integrated Microprocessors},
year={1992},
volume={E75-C},
number={10},
pages={1202-1211},
abstract={This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Performance Evaluation of a Translation Look-Aside Buffer for Highly Integrated Microprocessors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1202
EP - 1211
AU - Norio UTSUMI
AU - Akifumi NAGAO
AU - Tetsuro YOSHIMOTO
AU - Ryuichi YAMAGUCHI
AU - Jiro MIYAKE
AU - Hisakazu EDAMATSU
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 1992
AB - This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.
ER -
English
