Soft-Error Immune 180-µm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs
Summary :
This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.11 pp.1369-1376
- Publication Date
- 1992/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
Authors
Youji IDEI
Takeo SHIBA
Noriyuki HOMMA
Kunihiko YAMAGUCHI
Tohru NAKAMURA
Takahiro ONAI
Youichi TAMAKI
Yoshiaki SAKURAI
Keyword
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Youji IDEI, Takeo SHIBA, Noriyuki HOMMA, Kunihiko YAMAGUCHI, Tohru NAKAMURA, Takahiro ONAI, Youichi TAMAKI, Yoshiaki SAKURAI, "Soft-Error Immune 180-µm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 11, pp. 1369-1376, November 1992, doi: .
Abstract: This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_11_1369/_p
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@ARTICLE{e75-c_11_1369,
author={Youji IDEI, Takeo SHIBA, Noriyuki HOMMA, Kunihiko YAMAGUCHI, Tohru NAKAMURA, Takahiro ONAI, Youichi TAMAKI, Yoshiaki SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Soft-Error Immune 180-µm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs},
year={1992},
volume={E75-C},
number={11},
pages={1369-1376},
abstract={This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Soft-Error Immune 180-µm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1369
EP - 1376
AU - Youji IDEI
AU - Takeo SHIBA
AU - Noriyuki HOMMA
AU - Kunihiko YAMAGUCHI
AU - Tohru NAKAMURA
AU - Takahiro ONAI
AU - Youichi TAMAKI
AU - Yoshiaki SAKURAI
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1992
AB - This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.
ER -
English
