IEICE TRANSACTIONS on Electronics
Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel k-Ary Operation Circuits
Summary :
Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E76-C No.7 pp.1112-1118
- Publication Date
- 1993/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on New Architecture LSIs)
- Category
- Multiple-Valued Architectures and Systems
Authors
Keyword
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Saneaki TAMAKI, Michitaka KAMEYAMA, "Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel k-Ary Operation Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 7, pp. 1112-1118, July 1993, doi: .
Abstract: Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_7_1112/_p
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@ARTICLE{e76-c_7_1112,
author={Saneaki TAMAKI, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel k-Ary Operation Circuits},
year={1993},
volume={E76-C},
number={7},
pages={1112-1118},
abstract={Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel k-Ary Operation Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1112
EP - 1118
AU - Saneaki TAMAKI
AU - Michitaka KAMEYAMA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1993
AB - Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.
ER -
English
