Mathodology for Latchup-Free Design in Merged BiPMOSs
Summary :
The methodology for latchup-free design in bipolar and PMOS merged gates, so-called BiPMOS gates, is considered. Although BiPMOS gates can provide higher switching characteristics than conventional, individually drawn, BiCMOS gates even when the supply voltage is reduced, the general methodology to prevent latchup has been lacking. This paper presents an approximate, but sufficiently correct, mathematical technique to solve the Laplace equation, which gives the distribution of latchup trigger current for the given BiPMOS drawings. It is shown that the resistances of the collector plug and the spreading resistance under the base-collector junction greatly influence latchup, and that the well-emitter overlapping space becomes a problem in the case of a single collector. The distribution of latchup triggering current for the double-emitter double collector NPN transistor indicates the optimum position of the source diffusion area.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.10 pp.1668-1676
- Publication Date
- 1994/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Youichiro NIITSU, "Mathodology for Latchup-Free Design in Merged BiPMOSs" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 10, pp. 1668-1676, October 1994, doi: .
Abstract: The methodology for latchup-free design in bipolar and PMOS merged gates, so-called BiPMOS gates, is considered. Although BiPMOS gates can provide higher switching characteristics than conventional, individually drawn, BiCMOS gates even when the supply voltage is reduced, the general methodology to prevent latchup has been lacking. This paper presents an approximate, but sufficiently correct, mathematical technique to solve the Laplace equation, which gives the distribution of latchup trigger current for the given BiPMOS drawings. It is shown that the resistances of the collector plug and the spreading resistance under the base-collector junction greatly influence latchup, and that the well-emitter overlapping space becomes a problem in the case of a single collector. The distribution of latchup triggering current for the double-emitter double collector NPN transistor indicates the optimum position of the source diffusion area.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_10_1668/_p
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@ARTICLE{e77-c_10_1668,
author={Youichiro NIITSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Mathodology for Latchup-Free Design in Merged BiPMOSs},
year={1994},
volume={E77-C},
number={10},
pages={1668-1676},
abstract={The methodology for latchup-free design in bipolar and PMOS merged gates, so-called BiPMOS gates, is considered. Although BiPMOS gates can provide higher switching characteristics than conventional, individually drawn, BiCMOS gates even when the supply voltage is reduced, the general methodology to prevent latchup has been lacking. This paper presents an approximate, but sufficiently correct, mathematical technique to solve the Laplace equation, which gives the distribution of latchup trigger current for the given BiPMOS drawings. It is shown that the resistances of the collector plug and the spreading resistance under the base-collector junction greatly influence latchup, and that the well-emitter overlapping space becomes a problem in the case of a single collector. The distribution of latchup triggering current for the double-emitter double collector NPN transistor indicates the optimum position of the source diffusion area.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - Mathodology for Latchup-Free Design in Merged BiPMOSs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1668
EP - 1676
AU - Youichiro NIITSU
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 1994
AB - The methodology for latchup-free design in bipolar and PMOS merged gates, so-called BiPMOS gates, is considered. Although BiPMOS gates can provide higher switching characteristics than conventional, individually drawn, BiCMOS gates even when the supply voltage is reduced, the general methodology to prevent latchup has been lacking. This paper presents an approximate, but sufficiently correct, mathematical technique to solve the Laplace equation, which gives the distribution of latchup trigger current for the given BiPMOS drawings. It is shown that the resistances of the collector plug and the spreading resistance under the base-collector junction greatly influence latchup, and that the well-emitter overlapping space becomes a problem in the case of a single collector. The distribution of latchup triggering current for the double-emitter double collector NPN transistor indicates the optimum position of the source diffusion area.
ER -
English
