250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture

Yasuhiro TAKAI, Mamoru NAGASE, Mamoru KITAMURA, Yasuji KOSHIKAWA, Naoyuki YOSHIDA, Yasuaki KOBAYASHI, Takashi OBARA, Yukio FUKUZO, Hiroshi WATANABE

Summary :

A 3.3-V 512-k 18-b 2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as our conventional DRAM, has been achieved with 0.50-µm CMOS process technology.

• Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.756-761
• Publication Date: 1994/05/25
• Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

Authors

Yasuhiro TAKAI
Mamoru NAGASE
Mamoru KITAMURA
Yasuji KOSHIKAWA
Naoyuki YOSHIDA
Yasuaki KOBAYASHI
Takashi OBARA
Yukio FUKUZO
Hiroshi WATANABE

Keyword