A Stereo Asynchronous Digital Sample-Rate Converter for Digital Audio
Summary :
The design of an asynchronous digital sample-rate converter for digital-audio applications is presented. The theory of asynchronous sample-rate conversion is discussed using a signal-processing model that is based on highly interpolated input samples. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each output sample. Sample-rate ratio changes of up to 2:1 in either direction can be accommodated. The proposed signal-processing algorithm has been implemented in a 0.8-µm CMOS technology. Measurement results show excellent agreement with theory.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.811-818
- Publication Date
- 1994/05/25
- Publicized
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- Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
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Robert ADAMS, Tom KWAN, "A Stereo Asynchronous Digital Sample-Rate Converter for Digital Audio" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 5, pp. 811-818, May 1994, doi: .
Abstract: The design of an asynchronous digital sample-rate converter for digital-audio applications is presented. The theory of asynchronous sample-rate conversion is discussed using a signal-processing model that is based on highly interpolated input samples. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each output sample. Sample-rate ratio changes of up to 2:1 in either direction can be accommodated. The proposed signal-processing algorithm has been implemented in a 0.8-µm CMOS technology. Measurement results show excellent agreement with theory.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_811/_p
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@ARTICLE{e77-c_5_811,
author={Robert ADAMS, Tom KWAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Stereo Asynchronous Digital Sample-Rate Converter for Digital Audio},
year={1994},
volume={E77-C},
number={5},
pages={811-818},
abstract={The design of an asynchronous digital sample-rate converter for digital-audio applications is presented. The theory of asynchronous sample-rate conversion is discussed using a signal-processing model that is based on highly interpolated input samples. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each output sample. Sample-rate ratio changes of up to 2:1 in either direction can be accommodated. The proposed signal-processing algorithm has been implemented in a 0.8-µm CMOS technology. Measurement results show excellent agreement with theory.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - A Stereo Asynchronous Digital Sample-Rate Converter for Digital Audio
T2 - IEICE TRANSACTIONS on Electronics
SP - 811
EP - 818
AU - Robert ADAMS
AU - Tom KWAN
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - The design of an asynchronous digital sample-rate converter for digital-audio applications is presented. The theory of asynchronous sample-rate conversion is discussed using a signal-processing model that is based on highly interpolated input samples. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each output sample. Sample-rate ratio changes of up to 2:1 in either direction can be accommodated. The proposed signal-processing algorithm has been implemented in a 0.8-µm CMOS technology. Measurement results show excellent agreement with theory.
ER -
English
