A 40-mW 55 Mb/s CMOS Equalizer for Use in Magnetic Storage Read Channels
Summary :
A monolithic active equalizer in 2-µm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.819-829
- Publication Date
- 1994/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Patrick K. D. PAI, Asad A. ABIDI, "A 40-mW 55 Mb/s CMOS Equalizer for Use in Magnetic Storage Read Channels" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 5, pp. 819-829, May 1994, doi: .
Abstract: A monolithic active equalizer in 2-µm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_819/_p
Copy
@ARTICLE{e77-c_5_819,
author={Patrick K. D. PAI, Asad A. ABIDI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 40-mW 55 Mb/s CMOS Equalizer for Use in Magnetic Storage Read Channels},
year={1994},
volume={E77-C},
number={5},
pages={819-829},
abstract={A monolithic active equalizer in 2-µm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - A 40-mW 55 Mb/s CMOS Equalizer for Use in Magnetic Storage Read Channels
T2 - IEICE TRANSACTIONS on Electronics
SP - 819
EP - 829
AU - Patrick K. D. PAI
AU - Asad A. ABIDI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A monolithic active equalizer in 2-µm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations.
ER -
English
