A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC

Hae-Seung LEE

A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC

Hae-Seung LEE

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This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-µm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at2.5 V supplies. The active die area excluding the external logic circuit is 1 mm². Maximum DNL of 0.6 LSB and INL of 1 LSB at a 12-b resolution have been achieved.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.839-845

Publication Date: 1994/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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Hae-Seung LEE

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Hae-Seung LEE, "A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 5, pp. 839-845, May 1994, doi: .
Abstract: This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-µm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at2.5 V supplies. The active die area excluding the external logic circuit is 1 mm². Maximum DNL of 0.6 LSB and INL of 1 LSB at a 12-b resolution have been achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_839/_p

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@ARTICLE{e77-c_5_839,
author={Hae-Seung LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC},
year={1994},
volume={E77-C},
number={5},
pages={839-845},
abstract={This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-µm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at2.5 V supplies. The active die area excluding the external logic circuit is 1 mm². Maximum DNL of 0.6 LSB and INL of 1 LSB at a 12-b resolution have been achieved.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC
T2 - IEICE TRANSACTIONS on Electronics
SP - 839
EP - 845
AU - Hae-Seung LEE
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-µm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at2.5 V supplies. The active die area excluding the external logic circuit is 1 mm². Maximum DNL of 0.6 LSB and INL of 1 LSB at a 12-b resolution have been achieved.
ER -