IEICE TRANSACTIONS on Electronics
High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems
Summary :
In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes an very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.7 pp.1101-1107
- Publication Date
- 1994/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
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Yasuaki SAWANO, Bumchul KIM, Michitaka KAMEYAMA, "High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 7, pp. 1101-1107, July 1994, doi: .
Abstract: In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes an very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_7_1101/_p
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@ARTICLE{e77-c_7_1101,
author={Yasuaki SAWANO, Bumchul KIM, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems},
year={1994},
volume={E77-C},
number={7},
pages={1101-1107},
abstract={In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes an very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1101
EP - 1107
AU - Yasuaki SAWANO
AU - Bumchul KIM
AU - Michitaka KAMEYAMA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1994
AB - In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes an very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.
ER -
English
