IEICE TRANSACTIONS on Electronics
Design of a CAM-Based Collision Detection VLSI Processor for Robotics
Summary :
Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.7 pp.1108-1115
- Publication Date
- 1994/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
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Masanori HARIYAMA, Michitaka KANEYAMA, "Design of a CAM-Based Collision Detection VLSI Processor for Robotics" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 7, pp. 1108-1115, July 1994, doi: .
Abstract: Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_7_1108/_p
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@ARTICLE{e77-c_7_1108,
author={Masanori HARIYAMA, Michitaka KANEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a CAM-Based Collision Detection VLSI Processor for Robotics},
year={1994},
volume={E77-C},
number={7},
pages={1108-1115},
abstract={Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Design of a CAM-Based Collision Detection VLSI Processor for Robotics
T2 - IEICE TRANSACTIONS on Electronics
SP - 1108
EP - 1115
AU - Masanori HARIYAMA
AU - Michitaka KANEYAMA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1994
AB - Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.
ER -
English
