A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption
Summary :
This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.12 pp.1709-1716
- Publication Date
- 1995/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
- Category
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Katsuhiko UEDA, Toshio SUGIMURA, Toshihiro ISHIKAWA, Minoru OKAMOTO, Mikio SAKAKIHARA, Shinichi MARUI, "A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 12, pp. 1709-1716, December 1995, doi: .
Abstract: This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_12_1709/_p
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@ARTICLE{e78-c_12_1709,
author={Katsuhiko UEDA, Toshio SUGIMURA, Toshihiro ISHIKAWA, Minoru OKAMOTO, Mikio SAKAKIHARA, Shinichi MARUI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption},
year={1995},
volume={E78-C},
number={12},
pages={1709-1716},
abstract={This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption
T2 - IEICE TRANSACTIONS on Electronics
SP - 1709
EP - 1716
AU - Katsuhiko UEDA
AU - Toshio SUGIMURA
AU - Toshihiro ISHIKAWA
AU - Minoru OKAMOTO
AU - Mikio SAKAKIHARA
AU - Shinichi MARUI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1995
AB - This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm
ER -
English
