Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry

Hirotsugu KOJIMA; Satoshi TANAKA; Katsuro SASAKI

Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry

Hirotsugu KOJIMA, Satoshi TANAKA, Katsuro SASAKI

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We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V_DD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 µm CMOS device, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.680-683

Publication Date: 1995/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))

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Hirotsugu KOJIMA
Satoshi TANAKA
Katsuro SASAKI

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Hirotsugu KOJIMA, Satoshi TANAKA, Katsuro SASAKI, "Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 6, pp. 680-683, June 1995, doi: .
Abstract: We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V_DD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 µm CMOS device, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_6_680/_p

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@ARTICLE{e78-c_6_680,
author={Hirotsugu KOJIMA, Satoshi TANAKA, Katsuro SASAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry},
year={1995},
volume={E78-C},
number={6},
pages={680-683},
abstract={We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V_DD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 µm CMOS device, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry
T2 - IEICE TRANSACTIONS on Electronics
SP - 680
EP - 683
AU - Hirotsugu KOJIMA
AU - Satoshi TANAKA
AU - Katsuro SASAKI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V_DD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 µm CMOS device, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation.
ER -