IEICE TRANSACTIONS on Electronics
A Double-Leve1-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories
Summary :
In multilevel flash memorles, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, "A double-level-Vth select gate array architecture" to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.7 pp.1013-1020
- Publication Date
- 1996/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
- Category
- Memory
Authors
Keyword
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Ken TAKEUCHI, Tomoharu TANAKA, Hiroshi NAKAMURA, "A Double-Leve1-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 7, pp. 1013-1020, July 1996, doi: .
Abstract: In multilevel flash memorles, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, "A double-level-Vth select gate array architecture" to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_7_1013/_p
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@ARTICLE{e79-c_7_1013,
author={Ken TAKEUCHI, Tomoharu TANAKA, Hiroshi NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Double-Leve1-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories},
year={1996},
volume={E79-C},
number={7},
pages={1013-1020},
abstract={In multilevel flash memorles, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, "A double-level-Vth select gate array architecture" to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - A Double-Leve1-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 1013
EP - 1020
AU - Ken TAKEUCHI
AU - Tomoharu TANAKA
AU - Hiroshi NAKAMURA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1996
AB - In multilevel flash memorles, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, "A double-level-Vth select gate array architecture" to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized.
ER -
English
