IEICE TRANSACTIONS on Electronics
Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology
Summary :
An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E82-C No.9 pp.1730-1738
- Publication Date
- 1999/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
- Category
- Processors
Authors
Keyword
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Akira NAKADA, Masahiro KONDA, Tatsuo MORIMOTO, Takemi YONEZAWA, Tadashi SHIBATA, Tadahiro OHMI, "Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1730-1738, September 1999, doi: .
Abstract: An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1730/_p
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@ARTICLE{e82-c_9_1730,
author={Akira NAKADA, Masahiro KONDA, Tatsuo MORIMOTO, Takemi YONEZAWA, Tadashi SHIBATA, Tadahiro OHMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology},
year={1999},
volume={E82-C},
number={9},
pages={1730-1738},
abstract={An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1730
EP - 1738
AU - Akira NAKADA
AU - Masahiro KONDA
AU - Tatsuo MORIMOTO
AU - Takemi YONEZAWA
AU - Tadashi SHIBATA
AU - Tadahiro OHMI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm
ER -
English
