IEICE TRANSACTIONS on Electronics
A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
Summary :
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.11 pp.1716-1723
- Publication Date
- 2000/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
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Koji INOUE, Koji KAI, Kazuaki MURAKAMI, "A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1716-1723, November 2000, doi: .
Abstract: This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1716/_p
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@ARTICLE{e83-c_11_1716,
author={Koji INOUE, Koji KAI, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size},
year={2000},
volume={E83-C},
number={11},
pages={1716-1723},
abstract={This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
T2 - IEICE TRANSACTIONS on Electronics
SP - 1716
EP - 1723
AU - Koji INOUE
AU - Koji KAI
AU - Kazuaki MURAKAMI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.
ER -
English
