Low-Power Area-Efficient Design of Embedded High-Speed A/D Converters
Summary :
In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.11 pp.1724-1732
- Publication Date
- 2000/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
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Daisuke MIYAZAKI, Shoji KAWAHITO, "Low-Power Area-Efficient Design of Embedded High-Speed A/D Converters" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1724-1732, November 2000, doi: .
Abstract: In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1724/_p
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@ARTICLE{e83-c_11_1724,
author={Daisuke MIYAZAKI, Shoji KAWAHITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Area-Efficient Design of Embedded High-Speed A/D Converters},
year={2000},
volume={E83-C},
number={11},
pages={1724-1732},
abstract={In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Low-Power Area-Efficient Design of Embedded High-Speed A/D Converters
T2 - IEICE TRANSACTIONS on Electronics
SP - 1724
EP - 1732
AU - Daisuke MIYAZAKI
AU - Shoji KAWAHITO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.
ER -
English
