A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite

Eiji ARITA; Takashi FUJIWARA; Kin-ichiro NISHIYAMA; Akiko MAENO; Yasuo MATSUNAMI; Masahiko NAKAMURA; Hirohisa MACHIDA; Shuji MURAKAMI; Hiroyuki NAKAYAMA; Masahiko YOSHIMOTO

A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite

Eiji ARITA, Takashi FUJIWARA, Kin-ichiro NISHIYAMA, Akiko MAENO, Yasuo MATSUNAMI, Masahiko NAKAMURA, Hirohisa MACHIDA, Shuji MURAKAMI, Hiroyuki NAKAYAMA, Masahiko YOSHIMOTO

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A complete single chip multi-format Phase Shift Keying (PSK) demodulator ULSI for Japanese BS digital broadcasting is reported. The carrier recovery system shows the pull-in range up to +/-5 MHz. The clock recovery system cancels the poor group delay characteristic and the orthogonality degradation caused by the analog front end, and improves the BER performance by 0.2 dB. Thus the requirement to the analog front end is relaxed. A digital PLL ensures minimum program clock reference jitter in the output data stream, which simplifies jitter management in the succeeding MPEG2 system decoder. It integrates two 8-bit 60 MHz ADCs, 58 MHz VCO, 1 Mbit SRAM and the 450 K-gate FEC-demodulator core. Implementation of 1 Mbit de-interleaver RAM facilitates the use of a low cost receiver. The 8.8 milion transistor chip occupies the 72 mm² in a 0.25 µm triple-metal CMOS technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E84-C No.2 pp.166-174

Publication Date: 2001/02/01

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Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)

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Eiji ARITA, Takashi FUJIWARA, Kin-ichiro NISHIYAMA, Akiko MAENO, Yasuo MATSUNAMI, Masahiko NAKAMURA, Hirohisa MACHIDA, Shuji MURAKAMI, Hiroyuki NAKAYAMA, Masahiko YOSHIMOTO, "A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite" in IEICE TRANSACTIONS on Electronics, vol. E84-C, no. 2, pp. 166-174, February 2001, doi: .
Abstract: A complete single chip multi-format Phase Shift Keying (PSK) demodulator ULSI for Japanese BS digital broadcasting is reported. The carrier recovery system shows the pull-in range up to +/-5 MHz. The clock recovery system cancels the poor group delay characteristic and the orthogonality degradation caused by the analog front end, and improves the BER performance by 0.2 dB. Thus the requirement to the analog front end is relaxed. A digital PLL ensures minimum program clock reference jitter in the output data stream, which simplifies jitter management in the succeeding MPEG2 system decoder. It integrates two 8-bit 60 MHz ADCs, 58 MHz VCO, 1 Mbit SRAM and the 450 K-gate FEC-demodulator core. Implementation of 1 Mbit de-interleaver RAM facilitates the use of a low cost receiver. The 8.8 milion transistor chip occupies the 72 mm² in a 0.25 µm triple-metal CMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_166/_p

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@ARTICLE{e84-c_2_166,
author={Eiji ARITA, Takashi FUJIWARA, Kin-ichiro NISHIYAMA, Akiko MAENO, Yasuo MATSUNAMI, Masahiko NAKAMURA, Hirohisa MACHIDA, Shuji MURAKAMI, Hiroyuki NAKAYAMA, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite},
year={2001},
volume={E84-C},
number={2},
pages={166-174},
abstract={A complete single chip multi-format Phase Shift Keying (PSK) demodulator ULSI for Japanese BS digital broadcasting is reported. The carrier recovery system shows the pull-in range up to +/-5 MHz. The clock recovery system cancels the poor group delay characteristic and the orthogonality degradation caused by the analog front end, and improves the BER performance by 0.2 dB. Thus the requirement to the analog front end is relaxed. A digital PLL ensures minimum program clock reference jitter in the output data stream, which simplifies jitter management in the succeeding MPEG2 system decoder. It integrates two 8-bit 60 MHz ADCs, 58 MHz VCO, 1 Mbit SRAM and the 450 K-gate FEC-demodulator core. Implementation of 1 Mbit de-interleaver RAM facilitates the use of a low cost receiver. The 8.8 milion transistor chip occupies the 72 mm² in a 0.25 µm triple-metal CMOS technology.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite
T2 - IEICE TRANSACTIONS on Electronics
SP - 166
EP - 174
AU - Eiji ARITA
AU - Takashi FUJIWARA
AU - Kin-ichiro NISHIYAMA
AU - Akiko MAENO
AU - Yasuo MATSUNAMI
AU - Masahiko NAKAMURA
AU - Hirohisa MACHIDA
AU - Shuji MURAKAMI
AU - Hiroyuki NAKAYAMA
AU - Masahiko YOSHIMOTO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A complete single chip multi-format Phase Shift Keying (PSK) demodulator ULSI for Japanese BS digital broadcasting is reported. The carrier recovery system shows the pull-in range up to +/-5 MHz. The clock recovery system cancels the poor group delay characteristic and the orthogonality degradation caused by the analog front end, and improves the BER performance by 0.2 dB. Thus the requirement to the analog front end is relaxed. A digital PLL ensures minimum program clock reference jitter in the output data stream, which simplifies jitter management in the succeeding MPEG2 system decoder. It integrates two 8-bit 60 MHz ADCs, 58 MHz VCO, 1 Mbit SRAM and the 450 K-gate FEC-demodulator core. Implementation of 1 Mbit de-interleaver RAM facilitates the use of a low cost receiver. The 8.8 milion transistor chip occupies the 72 mm² in a 0.25 µm triple-metal CMOS technology.
ER -