200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology

Tatsuo TERUYAMA; Tetsuo KAMADA; Masashi SASAHARA; Shardul KAZI

200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology

Tatsuo TERUYAMA, Tetsuo KAMADA, Masashi SASAHARA, Shardul KAZI

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The strong demand for complex and high performance system-on-a-chip requires high performance microprocessor core and quick turn around design methodology. We have developed 128-bit synthesizable core processor and tile based quick turn around design methodology. It is 200 MHz MIPS compatible processor with 128-bit SIMD extension and is targeted for consumer electronics. We also developed an ASSP including the processor core, SDRAM controller, 2 PCI and 2 MAC mainly for network applications. For SOC development, we developed a tile based design methodology aiming at quick design convergence. The initial RTL design is synthesized and partitioned to several tiles by in-house tiling tool. It promises quick turn around from RTL design to tape out using the concurrency of the back-end design.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.2 pp.235-242

Publication Date: 2002/02/01

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)

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Tatsuo TERUYAMA, Tetsuo KAMADA, Masashi SASAHARA, Shardul KAZI, "200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 2, pp. 235-242, February 2002, doi: .
Abstract: The strong demand for complex and high performance system-on-a-chip requires high performance microprocessor core and quick turn around design methodology. We have developed 128-bit synthesizable core processor and tile based quick turn around design methodology. It is 200 MHz MIPS compatible processor with 128-bit SIMD extension and is targeted for consumer electronics. We also developed an ASSP including the processor core, SDRAM controller, 2 PCI and 2 MAC mainly for network applications. For SOC development, we developed a tile based design methodology aiming at quick design convergence. The initial RTL design is synthesized and partitioned to several tiles by in-house tiling tool. It promises quick turn around from RTL design to tape out using the concurrency of the back-end design.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_235/_p

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@ARTICLE{e85-c_2_235,
author={Tatsuo TERUYAMA, Tetsuo KAMADA, Masashi SASAHARA, Shardul KAZI, },
journal={IEICE TRANSACTIONS on Electronics},
title={200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology},
year={2002},
volume={E85-C},
number={2},
pages={235-242},
abstract={The strong demand for complex and high performance system-on-a-chip requires high performance microprocessor core and quick turn around design methodology. We have developed 128-bit synthesizable core processor and tile based quick turn around design methodology. It is 200 MHz MIPS compatible processor with 128-bit SIMD extension and is targeted for consumer electronics. We also developed an ASSP including the processor core, SDRAM controller, 2 PCI and 2 MAC mainly for network applications. For SOC development, we developed a tile based design methodology aiming at quick design convergence. The initial RTL design is synthesized and partitioned to several tiles by in-house tiling tool. It promises quick turn around from RTL design to tape out using the concurrency of the back-end design.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - 200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology
T2 - IEICE TRANSACTIONS on Electronics
SP - 235
EP - 242
AU - Tatsuo TERUYAMA
AU - Tetsuo KAMADA
AU - Masashi SASAHARA
AU - Shardul KAZI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - The strong demand for complex and high performance system-on-a-chip requires high performance microprocessor core and quick turn around design methodology. We have developed 128-bit synthesizable core processor and tile based quick turn around design methodology. It is 200 MHz MIPS compatible processor with 128-bit SIMD extension and is targeted for consumer electronics. We also developed an ASSP including the processor core, SDRAM controller, 2 PCI and 2 MAC mainly for network applications. For SOC development, we developed a tile based design methodology aiming at quick design convergence. The initial RTL design is synthesized and partitioned to several tiles by in-house tiling tool. It promises quick turn around from RTL design to tape out using the concurrency of the back-end design.
ER -