IEICE TRANSACTIONS on Electronics
A 500-MHz Embedded Out-of-Order Superscalar Microprocessor
Summary :
A MIPS-architecture-based embedded out-of-order superscalar microprocessor targeting broadband applications has been developed. Aggressive microarchitectures, such as superpipelining and out-of-order execution, have been applied to realize better performance scalability in order to fit with next-generation broadband applications. The chip includes a 32 K-Byte instruction cache, a 32 K-Byte data cache, 6 independent execution units, and has been designed using an ASIC-style design methodology on a 0.13-µm CMOS 5-layer aluminum technology. It can operate up to 500 MHz and achieves 1005 MIPS (Dhrystone 2.1) at 500-MHz operation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.2 pp.243-252
- Publication Date
- 2002/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
- Category
Authors
Masayuki DAITO
Kazumasa SUZUKI
Ken-ichi UEHIGASHI
Hiroshi MORITA
Hitoshi SONODA
Nobuhito MORIKAWA
Masatoshi MORIYAMA
Shoichiro SATO
Terumi FUKUDA
Saori NAKAMURA
Keyword
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Masayuki DAITO, Kazumasa SUZUKI, Ken-ichi UEHIGASHI, Hiroshi MORITA, Hitoshi SONODA, Nobuhito MORIKAWA, Masatoshi MORIYAMA, Shoichiro SATO, Terumi FUKUDA, Saori NAKAMURA, "A 500-MHz Embedded Out-of-Order Superscalar Microprocessor" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 243-252, February 2002, doi: .
Abstract: A MIPS-architecture-based embedded out-of-order superscalar microprocessor targeting broadband applications has been developed. Aggressive microarchitectures, such as superpipelining and out-of-order execution, have been applied to realize better performance scalability in order to fit with next-generation broadband applications. The chip includes a 32 K-Byte instruction cache, a 32 K-Byte data cache, 6 independent execution units, and has been designed using an ASIC-style design methodology on a 0.13-µm CMOS 5-layer aluminum technology. It can operate up to 500 MHz and achieves 1005 MIPS (Dhrystone 2.1) at 500-MHz operation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_243/_p
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@ARTICLE{e85-c_2_243,
author={Masayuki DAITO, Kazumasa SUZUKI, Ken-ichi UEHIGASHI, Hiroshi MORITA, Hitoshi SONODA, Nobuhito MORIKAWA, Masatoshi MORIYAMA, Shoichiro SATO, Terumi FUKUDA, Saori NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 500-MHz Embedded Out-of-Order Superscalar Microprocessor},
year={2002},
volume={E85-C},
number={2},
pages={243-252},
abstract={A MIPS-architecture-based embedded out-of-order superscalar microprocessor targeting broadband applications has been developed. Aggressive microarchitectures, such as superpipelining and out-of-order execution, have been applied to realize better performance scalability in order to fit with next-generation broadband applications. The chip includes a 32 K-Byte instruction cache, a 32 K-Byte data cache, 6 independent execution units, and has been designed using an ASIC-style design methodology on a 0.13-µm CMOS 5-layer aluminum technology. It can operate up to 500 MHz and achieves 1005 MIPS (Dhrystone 2.1) at 500-MHz operation.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A 500-MHz Embedded Out-of-Order Superscalar Microprocessor
T2 - IEICE TRANSACTIONS on Electronics
SP - 243
EP - 252
AU - Masayuki DAITO
AU - Kazumasa SUZUKI
AU - Ken-ichi UEHIGASHI
AU - Hiroshi MORITA
AU - Hitoshi SONODA
AU - Nobuhito MORIKAWA
AU - Masatoshi MORIYAMA
AU - Shoichiro SATO
AU - Terumi FUKUDA
AU - Saori NAKAMURA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - A MIPS-architecture-based embedded out-of-order superscalar microprocessor targeting broadband applications has been developed. Aggressive microarchitectures, such as superpipelining and out-of-order execution, have been applied to realize better performance scalability in order to fit with next-generation broadband applications. The chip includes a 32 K-Byte instruction cache, a 32 K-Byte data cache, 6 independent execution units, and has been designed using an ASIC-style design methodology on a 0.13-µm CMOS 5-layer aluminum technology. It can operate up to 500 MHz and achieves 1005 MIPS (Dhrystone 2.1) at 500-MHz operation.
ER -
English
